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www.motorola.com/semiconductors m68hc05 microcontrollers mc68hc705j1a/d rev. 4, 5/2002 mc68hc705j1a mc68hrc705j1a technical data mc68hsc705j1a mc68hsr705j1a

mc68hc705j1a ? rev. 4.0 technical data motorola 3 mc68hc705j1a mc68hrc705j1a mc68hsc705j1a mc68hsr705j1a technical data to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digital dna is a trademark of motorola, inc. ? motorola, inc., 2002
technical data mc68hc705j1a ? rev. 4.0 4 motorola technical data revision history date revision level description page number(s) may, 2002 4.0 figure 2-2. i/o register summary ? corrected reset state for l a s t en t ry ( m a s k op t i on reg i s t er) 3 7 figure 2-4. mask option register (mor) ? corrected reset state 41 6.3.3 pulldown register a ? corrected note 91 6.4.3 pulldown register b ? corrected note 94
mc68hc705j1a ? rev. 4.0 technical data motorola list of sections 5 technical data ? mc68hc705j1a list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 21 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 section 3. central processor unit (cpu) . . . . . . . . . . . . 45 section 4. resets and interrupts . . . . . . . . . . . . . . . . . . . 69 section 5. low-power modes. . . . . . . . . . . . . . . . . . . . . . 79 section 6. parallel input/output (i/o) ports . . . . . . . . . . 87 section 7. computer operating properly (cop) module . . . . . . . . . . . . . . . . . . . . . . . . . 97 section 8. external interrupt module (irq) . . . . . . . . . . 101 section 9. multifunction timer module . . . . . . . . . . . . . 109 section 10. electrical specifications . . . . . . . . . . . . . . . 117 section 11. mechanical specifications . . . . . . . . . . . . . 131 section 12. ordering information . . . . . . . . . . . . . . . . . 135 appendix a. mc68hrc705j1a . . . . . . . . . . . . . . . . . . . 137 appendix b. mc68hsc705j1a . . . . . . . . . . . . . . . . . . . 141 appendix c. mc68hsr705j1a . . . . . . . . . . . . . . . . . . . 145 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
technical data mc68hc705j1a ? rev. 4.0 6 list of sections motorola list of sections
mc68hc705j1a ? rev. 4.0 technical data motorola table of contents 7 technical data ? mc68hc705j1a table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.2 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.5.2.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2.2 ceramic resonator oscillator . . . . . . . . . . . . . . . . . . . . . 28 1.5.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7 irq /v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.8 pa0 ? pa7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.9 pb0 ? pb5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.4 input/output register summary . . . . . . . . . . . . . . . . . . . . . . . .35 2.5 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
technical data mc68hc705j1a ? rev. 4.0 8 table of contents motorola table of contents 2.6 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.6.1 eprom/otprom programming . . . . . . . . . . . . . . . . . . . . .38 2.6.2 eprom programming register . . . . . . . . . . . . . . . . . . . . .39 2.6.3 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.7 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 eprom programming characteristics . . . . . . . . . . . . . . . . . . .43 section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.3 cpu control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 arithmetic/logic unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.7 indexed, 16-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.6.1.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.6.2 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.6.2.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . .55 3.6.2.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . .56 3.6.2.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . .57 3.6.2.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . .59 3.6.2.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
table of contents mc68hc705j1a ? rev. 4.0 technical data motorola table of contents 9 3.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 section 4. resets and interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 4.3 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.3.3 cop watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.3.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.2 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.3 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.4.3.1 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.4.3.2 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . .76 4.4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 section 5. low-power modes 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.3 exiting stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.4 effects of stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.2 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.4.3 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.4.4 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.4.5 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.4.6 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
technical data mc68hc705j1a ? rev. 4.0 10 table of contents motorola table of contents section 6. parallel input/output (i/o) ports 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 6.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.3 pulldown register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.3.4 port a led drive capability . . . . . . . . . . . . . . . . . . . . . . . . .92 6.3.5 port a i/o pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 6.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 6.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.4.3 pulldown register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 6.5 5.0-volt i/o port electrical characteristics . . . . . . . . . . . . . . . . 95 6.6 3.3-volt i/o port electrical characteristics . . . . . . . . . . . . . . . . 95 section 7. computer operating properly (cop) module 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.3.1 cop watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.3.2 cop watchdog timeout period . . . . . . . . . . . . . . . . . . . . . .98 7.3.3 clearing the cop watchdog . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
table of contents mc68hc705j1a ? rev. 4.0 technical data motorola table of contents 11 section 8. external interrupt module (irq) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8.3.1 irq /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 8.3.2 optional external interrupts . . . . . . . . . . . . . . . . . . . . . . . .104 8.4 irq status and control register . . . . . . . . . . . . . . . . . . . . . .106 8.5 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.5.1 5.0-volt external interrupt timing characteristics . . . . . . .107 8.5.2 3.3-volt external interrupt timing characteristics . . . . . . .107 section 9. multifunction timer module 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 9.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 9.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.5 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.5.1 timer status and control register . . . . . . . . . . . . . . . . . . .112 9.5.2 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 section 10. electrical specifications 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 10.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .119 10.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
technical data mc68hc705j1a ? rev. 4.0 12 table of contents motorola table of contents 10.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 10.7 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .121 10.8 3.3-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . 122 10.9 driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.10 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.11 eprom programming characteristics . . . . . . . . . . . . . . . . . .126 10.12 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 10.13 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 section 11. mechanical specifications 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 11.3 plastic dual in-line package (case 738) . . . . . . . . . . . . . . . .132 11.4 small outline integrated circuit (case 751) . . . . . . . . . . . . . .132 11.5 ceramic dual in-line package (case 732) . . . . . . . . . . . . . .133 section 12. ordering information 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 12.3 mcu order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 appendix a. mc68hrc705j1a a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 a.3 rc oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 a.4 typical internal operating frequency for rc oscillator option. . . . . . . . . . . . . . . . . . . . . . . . . . .139 a.5 package types and order numbers . . . . . . . . . . . . . . . . . . .140
table of contents mc68hc705j1a ? rev. 4.0 technical data motorola table of contents 13 appendix b. mc68hsc705j1a b.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 b.3 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .142 b.4 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .142 b.5 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 b.6 package types and order numbers . . . . . . . . . . . . . . . . . . .144 appendix c. mc68hsr705j1a c.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 c.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 c.3 rc oscillator connections (external resistor). . . . . . . . . . . . 145 c.4 typical internal operating frequency at 25 c for high-speed rc oscillator option. . . . . . . . . . . . . . . . . 146 c.5 rc oscillator connections (no external resistor) . . . . . . . . .147 c.6 typical internal operating frequency versus temperature (no external resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 c.7 package types and order numbers . . . . . . . . . . . . . . . . . . .149 index index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
technical data mc68hc705j1a ? rev. 4.0 14 table of contents motorola table of contents
mc68hc705j1a ? rev. 4.0 technical data motorola list of figures 15 technical data ? mc68hc705j1a list of figures figure title page 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1-2 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1-3 bypassing layout recommendation . . . . . . . . . . . . . . . . . .26 1-4 crystal connections with oscillator internal resistor mask option . . . . . . . . . . . . . 28 1-5 crystal connections without oscillator internal resistor mask option . . . . . . . . . . . . . 28 1-6 ceramic resonator connections with oscillator internal resistor mask option . . . . . . . . . 29 1-7 ceramic resonator connections without oscillator internal resistor mask option. . . . . . .29 1-8 external clock connections . . . . . . . . . . . . . . . . . . . . . . . . . 30 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2-3 eprom programming register (eprog). . . . . . . . . . . . . .39 2-4 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . .41 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3-3 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 50 4-1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4-2 power-on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
technical data mc68hc705j1a ? rev. 4.0 16 list of figures motorola list of figures figure title page 4-3 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4-4 external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 4-5 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . .75 4-6 interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4-7 interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5-1 stop mode recovery timing . . . . . . . . . . . . . . . . . . . . . . . .85 5-2 stop/halt/wait flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6-1 parallel i/o port register summary . . . . . . . . . . . . . . . . . . .88 6-2 port a data register (porta). . . . . . . . . . . . . . . . . . . . . . .89 6-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . .90 6-4 port a i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 6-5 pulldown register a (pdra) . . . . . . . . . . . . . . . . . . . . . . . .91 6-6 port b data register (portb). . . . . . . . . . . . . . . . . . . . . . .92 6-7 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . .93 6-8 port b i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 6-9 pulldown register b (pdrb) . . . . . . . . . . . . . . . . . . . . . . . .94 7-1 cop register (copr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . .102 8-2 interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8-3 irq status and control register (iscr) . . . . . . . . . . . . . .106 8-4 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . .107 9-1 multifunction timer block diagram. . . . . . . . . . . . . . . . . . .110 9-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 9-3 timer status and control register (tscr) . . . . . . . . . . . .112 9-4 timer counter register (tcr) . . . . . . . . . . . . . . . . . . . . . .114
list of figures mc68hc705j1a ? rev. 4.0 technical data motorola list of figures 17 figure title page 10-1 pa0 ? pa7, pb0 ? pb5 typical high-side driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .123 10-2 pa0 ? pa3, pb0 ? pb5 typical low-side driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .123 10-3 pa4 ? pa7 typical low-side driver characteristics . . . . . . 124 10-4 typical operating i dd (25 c) . . . . . . . . . . . . . . . . . . . . . . .125 10-5 typical wait mode i dd (25 c) . . . . . . . . . . . . . . . . . . . . . . 125 10-6 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . .128 10-7 stop mode recovery timing . . . . . . . . . . . . . . . . . . . . . . .128 10-8 power-on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . .129 10-9 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 a-1 rc oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . 138 a-2 typical internal operating frequency for various v dd at 25 c ? rc oscillator option only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 b-1 typical high-speed operating i dd (25 c) . . . . . . . . . . . . . 142 b-2 typical high-speed wait mode i dd (25 c) . . . . . . . . . . . . 143 c-1 typical internal operating frequency at 25 c for high-speed rc oscillator option . . . . . . . .146 c-2 rc oscillator connections (no external resistor) . . . . . . . 147 c-3 typical internal operating frequency versus temperature (oscres bit = 1) . . . . . . . . . . . .148
technical data mc68hc705j1a ? rev. 4.0 18 list of figures motorola list of figures
mc68hc705j1a ? rev. 4.0 technical data motorola list of tables 19 technical data ? mc68hc705j1a list of tables table title page 1-1 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . .55 3-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . .56 3-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . .58 3-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . .59 3-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4-1 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4-2 external interrupt timing (v dd = 5.0 vdc) . . . . . . . . . . . . . . .75 4-3 external interrupt timing (v dd = 3.3 vdc) . . . . . . . . . . . . . . .75 4-4 reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . .77 6-1 port a pin operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6-2 port b pin operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 9-1 real-time interrupt rate selection . . . . . . . . . . . . . . . . . . .114 12-1 order numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 a-1 mc68hrc705j1a (rc oscillator option) order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 b-1 mc68hsc705j1a (high speed) order numbers . . . . . . . .144 c-1 mc68hsr705j1a (high-speed rc oscillator option) order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
technical data mc68hc705j1a ? rev. 4.0 20 list of tables motorola list of tables
mc68hc705j1a ? rev. 4.0 technical data motorola general description 21 technical data ? mc68hc705j1a section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.2 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.5.2.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2.2 ceramic resonator oscillator . . . . . . . . . . . . . . . . . . . . . 28 1.5.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7 irq /v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.8 pa0 ? pa7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.9 pb0 ? pb5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
technical data mc68hc705j1a ? rev. 4.0 22 general description motorola general description 1.2 introduction the mc68hc705j1a is a member of motorola ? s low-cost, high-performance m68hc05 family of 8-bit microcontroller units (mcus). the m68hc05 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the popular m68hc05 central processor unit (cpu) and are available with a variety of subsystems, memory sizes and types, and package types. on-chip memory of the mc68hc705j1a includes 1240 bytes of erasable, programmable read-only memory (eprom). in packages without the transparent window for eprom erasure, the 1240 eprom bytes serve as one-time programmable read-only memory (otprom). the mc68hrc705j1a is a resistor-capacitor (rc) oscillator mask option version of the mc68hc705j1a and is discussed in appendix a. mc68hrc705j1a . a high-speed version of the mc68hc705j1a, the mc68hsc705j1a, is discussed in appendix b. mc68hsc705j1a . the mc68hsr705j1a, discussed in appendix c. mc68hsr705j1a , is a high-speed version of the mc68hrc705j1a. a functional block diagram of the mc68hc705j1a is shown in figure 1-1 .
general description introduction mc68hc705j1a ? rev. 4.0 technical data motorola general description 23 figure 1-1. block diagram 0000000011 watchdog and illegal address detect static ram (sram) ? 64 bytes alu cpu control 68hc05 cpu accumulator index register stk ptr program counter condition code register 15-stage multifunction timer system divide internal oscillator osc1 osc2 cpu registers user eprom ? 1240 bytes mask option register (eprom) *10-ma sink capability **external interrupt capability data direction register a data direction register b port a port b pb5 pb4 pb3 pb2 pb1 pb0 pa7* pa6* pa5* pa4* pa3** pa2** pa1** pa0** 111hinzc by 32 reset irq /v pp
technical data mc68hc705j1a ? rev. 4.0 24 general description motorola general description 1.3 features features of the mc68hc705j1a include: peripheral modules: ? 15-stage multifunction timer ? computer operating properly (cop) watchdog 14 bidirectional input/output (i/o) lines, including: ? 10-ma sink capability on four i/o pins ? mask option register (mor) and software programmable pulldowns on all i/o pins ? mor selectable interrupt on four i/o pins, a keyboard scan feature mor selectable sensitivity on external interrupt (edge- and level-sensitive or edge-sensitive only) on-chip oscillator with connections for: ? crystal ? ceramic resonator ? resistor-capacitor (rc) oscillator ? external clock 1240 bytes of eprom/otprom, including eight bytes for user vectors 64 bytes of user random-access memory (ram) memory-mapped i/o registers fully static operation with no minimum clock speed power-saving stop, halt, wait, and data-retention modes external interrupt mask bit and acknowledge bit illegal address reset internal steering diode and pullup resistor from reset pin to v dd
general description programmable options mc68hc705j1a ? rev. 4.0 technical data motorola general description 25 1.4 programmable options the options in table 1-1 are programmable in the mask option register (mor). 1.5 pin assignments figure 1-2 shows the mc68hc705j1a pin assignments. 1.5.1 v dd and v ss v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins, placing high, short-duration current demands on the power supply. to prevent noise problems, take special care as figure 1-3 shows, by placing the bypass capacitors as close as possible to the mcu. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. table 1-1. programmable options feature option cop watchdog timer enabled or disabled external interrupt triggering edge-sensitive only or edge- and level-sensitive port a irq pin interrupts enabled or disabled port pulldown resistors enabled or disabled stop instruction mode stop mode or halt mode crystal oscillator internal resistor enabled or disabled eprom security enabled or disabled short oscillator delay counter enabled or disabled
technical data mc68hc705j1a ? rev. 4.0 26 general description motorola general description figure 1-2. pin assignments figure 1-3. bypassing layout recommendation osc1 1 osc2 2 pb5 3 pb4 4 pb3 5 pb2 6 pb1 7 pb0 8 reset 20 irq /v pp 19 pa0 18 pa1 17 pa2 16 pa3 15 pa4 14 pa5 13 pa6 12 pa7 11 v ss 10 v dd 9 c1 c2 mcu c1 0.1 f c2 v+ + v dd v ss v dd v ss
general description pin assignments mc68hc705j1a ? rev. 4.0 technical data motorola general description 27 1.5.2 osc1 and osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. the oscillator can be driven by any of these: 1. crystal (see figure 1-4 and figure 1-5 .) 2. ceramic resonator (see figure 1-6 and figure 1-7 .) 3. resistor/capacitor (rc) oscillator (refer to appendix a. mc68hrc705j1a and appendix c. mc68hsr705j1a .) 4. external clock signal (see figure 1-8 .) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . 1.5.2.1 crystal oscillator figure 1-4 and figure 1-5 show a typical crystal oscillator circuit for an at-cut, parallel resonant crystal. follow the crystal supplier ? s recommendations, as the crystal parameters determine the external component values required to provide reliable startup and maximum stability. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the crystal and capacitors as close as possible to the pins. an internal startup resistor of approximately 2m ? is provided between osc1 and osc2 for the crystal oscillator as a programmable mask option. note: use an at-cut crystal and not an at-strip crystal because the mcu can overdrive an at-strip crystal.
technical data mc68hc705j1a ? rev. 4.0 28 general description motorola general description figure 1-4. crystal connections with oscillator internal resistor mask option figure 1-5. crystal connections without oscillator internal resistor mask option 1.5.2.2 ceramic resonator oscillator to reduce cost, use a ceramic resonator instead of the crystal. the circuits shown in figure 1-6 and figure 1-7 show ceramic resonator circuits. follow the resonator manufacturer ? s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. mcu c1 c2 xtal c4 c3 xtal c3 27 pf c4 27 pf osc1 osc2 osc1 osc2 v ss v dd v ss mcu c1 c2 r xtal c4 c3 r 10 m ? ? xtal c3 27 pf c4 27 pf osc1 osc2 v dd v ss osc1 osc2 v ss
general description pin assignments mc68hc705j1a ? rev. 4.0 technical data motorola general description 29 mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. an internal startup resistor of approximately 2 m ? is provided between osc1 and osc2 as a programmable mask option. figure 1-6. ceramic resonator connections with oscillator internal resistor mask option figure 1-7. ceramic resonator connections without oscillator internal resistor mask option mcu c1 c2 ceramic c4 c3 ceramic c3 27 pf c4 27 pf resonator resonator osc1 osc2 osc1 osc2 v dd v ss v ss mcu c1 c2 r ceramic c4 c3 r 10 m ? ? ceramic c3 27 pf c4 27 pf resonator resonator v ss v dd v ss osc1 osc2 osc1 osc2
technical data mc68hc705j1a ? rev. 4.0 30 general description motorola general description 1.5.2.3 rc oscillator refer to appendix a. mc68hrc705j1a and appendix c. mc68hsr705j1a . 1.5.2.4 external clock an external clock from another complementary metal-oxide semiconductor (cmos)-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-8 . this configuration is possible regardless of whether the crystal/ceramic resonator or the rc oscillator is enabled. figure 1-8. external clock connections 1.6 reset applying a logic 0 to the reset pin forces the mcu to a known startup state. an internal reset also pulls the reset pin low. an internal resistor to v dd pulls the reset pin high. a steering diode between the reset and v dd pins discharges any reset pin voltage when power is removed from the mcu. the reset pin contains an internal schmitt trigger to improve its noise immunity as an input. refer to section 4. resets and interrupts for more information. mcu external cmos clock osc1 osc2
general description irq/v pp mc68hc705j1a ? rev. 4.0 technical data motorola general description 31 1.7 irq /v pp the external interrupt/programming voltage pin (irq /v pp ) drives the asynchronous irq interrupt function of the cpu. additionally, it is used to program the user eprom and mask option register. (see section 2. memory and section 8. external interrupt module (irq) .) the level bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. if level-sensitive triggering is selected, the irq /v pp input requires an external resistor to v dd for wired-or operation. if the irq /v pp pin is not used, it must be tied to the v dd supply. the irq /v pp pin contains an internal schmitt trigger as part of its input to improve noise immunity. the voltage on this pin should not exceed v dd except when the pin is being used for programming the eprom. note: the mask option register can enable the pa0 ? pa3 pins to function as external interrupt pins. 1.8 pa0 ? pa7 these eight input/output (i/o) lines comprise port a, a general-purpose, bidirectional i/o port. see section 8. external interrupt module (irq) for information on pa0 ? pa3 external interrupts. 1.9 pb0 ? pb5 these six i/o lines comprise port b, a general-purpose, bidirectional i/o port.
technical data mc68hc705j1a ? rev. 4.0 32 general description motorola general description
mc68hc705j1a ? rev. 4.0 technical data motorola memory 33 technical data ? mc68hc705j1a section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.4 input/output register summary . . . . . . . . . . . . . . . . . . . . . . . .35 2.5 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.6.1 eprom/otprom programming . . . . . . . . . . . . . . . . . . . . .38 2.6.2 eprom programming register . . . . . . . . . . . . . . . . . . . . .39 2.6.3 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.7 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 eprom programming characteristics . . . . . . . . . . . . . . . . . . .43 2.2 introduction this section describes the organization of the on-chip memory consisting of: 1232 bytes of user erasable, programmable read-only memory (eprom), plus eight bytes for user vectors 64 bytes of user random-access memory (ram)
technical data mc68hc705j1a ? rev. 4.0 34 memory motorola memory 2.3 memory map port a data register (porta) $0000 port b data register (portb) $0001 unimplemented $0002 $0003 data direction register a (ddra) $0004 data direction register b (ddrb) $0005 unimplemented $0006 $0007 timer status and control register (tscr) $0008 timer control register (tcr) $0009 $0000 i/o registers 32 bytes irq status and control register (iscr) $000a unimplemented $000b $001f $0020 unimplemented 160 bytes $000f pulldown register port a (pdra) $0010 $00bf pulldown register port b (pdrb) $0011 $00c0 ram 64 bytes unimplemented $0012 $00ff $0017 $0100 unimplemented 512 bytes eprom programming register (eprog) $0018 unimplemented $0019 $02ff $0300 eprom 1232 bytes $001e reserved $001f $07cf $07d0 unimplemented 30 bytes cop register (copr) (1) $07f0 mask option register (mor) $07f1 $07ed reserved $07f2 $07ee test rom 2 bytes $07ef $07f7 $07f0 registers and eprom 16 bytes timer interrupt vector high $07f8 timer interrupt vector low $07f9 $07ff external interrupt vector high $07fa external interrupt vector low $07fb software interrupt vector high $07fc software interrupt vector low $07fd reset vector high $07fe reset vector low $07ff (1) writing to bit 0 of $07f0 clears the computer operating properly (cop) watchdog. figure 2-1. memory map
memory input/output register summary mc68hc705j1a ? rev. 4.0 technical data motorola memory 35 2.4 input/output register summary addr.register name bit 7654321bit 0 $0000 port a data register (porta) see page 89. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 92. read: 0 0 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0002 unimplemented $0003 unimplemented $0004 data direction register a (ddra) see page 90. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 93. read: 0 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 unimplemented $0007 unimplemented $0008 timer status and control register (tscr) see page 112. read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 = unimplemented r = reserved figure 2-2. i/o register summary (sheet 1 of 3)
technical data mc68hc705j1a ? rev. 4.0 36 memory motorola memory $0009 timer counter register (tcr) see page 114. read: tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 write: reset:00000000 $000a irq status and control register (iscr) see page 106. read: irqe 000irqf000 write: r irqr reset:10000000 $000b unimplemented $000f unimplemented $0010 pulldown register a (pdra) see page 91. read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 $0011 pulldown register b (pdrb) see page 94. read: write: pdib5 pdib4 pdib3 pdib2 pdib1 pdib0 reset:00000000 $0012 unimplemented $0017 unimplemented $0018 eprom programming register (eprog) see page 39. read: 0 0 0 0 0 elat mpgm epgm write: rrrr reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. i/o register summary (sheet 2 of 3)
memory ram mc68hc705j1a ? rev. 4.0 technical data motorola memory 37 2.5 ram the 64 addresses from $00c0 to $00ff serve as both the user ram and the stack ram. before processing an interrupt, the central processor unit (cpu) uses five bytes of the stack to save the contents of the cpu registers. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements when the cpu stores a byte on the stack and increments when the cpu retrieves a byte from the stack. note: be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. $0019 unimplemented $001e unimplemented $001f reserved rrrrrrrr $07f0 cop register (copr) see page 99. read: write: copc reset: 0 $07f1 mask option register (mor) see page 41. read: soscd epmsec oscres swait swpdi pirq level copen write: reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. i/o register summary (sheet 3 of 3)
technical data mc68hc705j1a ? rev. 4.0 38 memory motorola memory 2.6 eprom/otprom a microcontroller unit (mcu) with a quartz window has 1240 bytes of erasable, programmable rom (eprom). the quartz window allows eprom erasure with ultraviolet light. note: keep the quartz window covered with an opaque material except when programming the mcu. ambient light can affect mcu operation. in an mcu without the quartz window, the eprom cannot be erased and serves as 1240 bytes of one-time programmable rom (otprom). these addresses are user eprom/otprom locations: $0300 ? $07cf $07f8 ? $07ff, used for user-defined interrupt and reset vectors the computer operating properly (cop) register (copr) is an eprom/otprom location at address $07f0. the mask option register (mor) is an eprom/otprom location at address $07f1. 2.6.1 eprom/otprom programming the two ways to program the eprom/otprom are: 1. manipulating the control bits in the eprom programming register to program the eprom/otprom on a byte-by-byte basis 2. programming the eprom/otprom with the m68hc705j in-circuit simulator (m68hc705jics) available from motorola
memory eprom/otprom mc68hc705j1a ? rev. 4.0 technical data motorola memory 39 2.6.2 eprom programming register the eprom programming register (eprog) contains the control bits for programming the eprom/otprom. elat ? eprom bus latch bit this read/write bit latches the address and data buses for eprom/otprom programming. clearing the elat bit automatically clears the epgm bit. eprom/otprom data cannot be read while the elat bit is set. reset clears the elat bit. 1 = address and data buses configured for eprom/otprom programming the eprom 0 = address and data buses configured for normal operation mpgm ? mor programming bit this read/write bit applies programming power from the irq /v pp pin to the mask option register. reset clears mpgm. 1 = programming voltage applied to mor 0 = programming voltage not applied to mor epgm ? eprom programming bit this read/write bit applies the voltage from the irq /v pp pin to the eprom. to write the epgm bit, the elat bit must be set already. reset clears epgm. 1 = programming voltage (irq /v pp pin) applied to eprom 0 = programming voltage (irq /v pp pin) not applied to eprom address: $0018 bit 7654321bit 0 read: 0 0 0 0 0 elat mpgm epgm write: rrrr reset:00000000 = unimplemented r = reserved figure 2-3. eprom programming register (eprog)
technical data mc68hc705j1a ? rev. 4.0 40 memory motorola memory note: writing logic 1s to both the elat and epgm bits with a single instruction sets elat and clears epgm. elat must be set first by a separate instruction. bits [7:3] ? reserved take these steps to program a byte of eprom/otprom: 1. apply the programming voltage, v pp , to the irq /v pp pin. 2. set the elat bit. 3. write to any eprom/otprom address. 4. set the epgm bit and wait for a time, t epgm . 5. clear the elat bit. 2.6.3 eprom erasing the erased state of an eprom bit is logic 0. erase the eprom by exposing it to 15 ws/cm 2 of ultraviolet light with a wave length of 2537 angstroms. position the ultraviolet light source one inch from the eprom. do not use a shortwave filter. 2.7 mask option register the mask option register (mor) is an eprom/otprom byte that controls these options: cop watchdog (enable or disable) external interrupt pin triggering (edge-sensitive only or edge- and level-sensitive) port a external interrupts (enable or disable) port pulldown resistors (enable or disable) stop instruction (stop mode or halt mode) crystal oscillator internal resistor (enable or disable) eprom security (enable or disable) short oscillator delay (enable or disable)
memory mask option register mc68hc705j1a ? rev. 4.0 technical data motorola memory 41 take these steps to program the mask option register: 1. apply the programming voltage, v pp , to the irq /v pp pin. 2. write to the mor. 3. set the mpgm bit and wait for a time, t mpgm . 4. clear the mpgm bit. 5. reset the mcu. soscd ? short oscillator delay bit the soscd bit controls the oscillator stabilization counter. the normal stabilization delay following reset or exit from stop mode is 4064 t cyc . setting soscd enables a short oscillator stabilization delay. 1 = short oscillator delay enabled 0 = short oscillator delay disabled epmsec ? eprom security bit the epmsec bit controls access to the eprom/otprom. 1 = external access to eprom/otprom denied 0 = external access to eprom/otprom not denied oscres ? oscillator internal resistor bit the oscres bit enables a 2-m ? internal resistor in the oscillator circuit. 1 = oscillator internal resistor enabled 0 = oscillator internal resistor disabled note: program the oscres bit to logic 0 in devices using rc oscillators. address: $07f1 bit 7654321bit 0 read: soscd epmsec oscres swait swpdi pirq level copen write: reset: unaffected by reset figure 2-4. mask option register (mor)
technical data mc68hc705j1a ? rev. 4.0 42 memory motorola memory swait ? stop-to-wait conversion bit the swait bit enables halt mode. when the swait bit is set, the cpu interprets the stop instruction as a wait instruction, and the mcu enters halt mode. halt mode is the same as wait mode, except that an oscillator stabilization delay of 1 to 4064 t cyc occurs after exiting halt mode. 1 = halt mode enabled 0 = halt mode not enabled swpdi ? software pulldown inhibit bit the swpdi bit inhibits software control of the i/o port pulldown devices. the swpdi bit overrides the pulldown inhibit bits in the port pulldown inhibit registers. 1 = software pulldown control inhibited 0 = software pulldown control not inhibited pirq ? port a external interrupt bit the pirq bit enables the pa0 ? pa3 pins to function as external interrupt pins. 1 = pa0 ? pa3 enabled as external interrupt pins 0 = pa0 ? pa3 not enabled as external interrupt pins level ? external interrupt sensitivity bit the level bit controls external interrupt triggering sensitivity. 1 = external interrupts triggered by active edges and active levels 0 = external interrupts triggered only by active edges copen ? cop enable bit the copen bit enables the cop watchdog. 1 = cop watchdog enabled 0 = cop watchdog disabled
memory eprom programming characteristics mc68hc705j1a ? rev. 4.0 technical data motorola memory 43 2.8 eprom programming characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c symbol min typ max unit programming voltage irq /v pp v pp 16.0 16.5 17.0 v programming current irq /v pp i pp ?| 3.0 10.0 ma programming time per array byte mor t epgm t mpgm 4 4 ? ? ? ? ms
technical data mc68hc705j1a ? rev. 4.0 44 memory motorola memory
mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 45 technical data ? mc68hc705j1a section 3. central processor unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.3 cpu control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 arithmetic/logic unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.6.1.7 indexed, 16-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.6.1.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.6.2 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.6.2.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . .55 3.6.2.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . .56 3.6.2.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . .57 3.6.2.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . .59 3.6.2.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
technical data mc68hc705j1a ? rev. 4.0 46 central processor unit (cpu) motorola central processor unit (cpu) 3.2 introduction the central processor unit (cpu) consists of a cpu control unit, an arithmetic/logic unit (alu), and five cpu registers. the cpu control unit fetches and decodes instructions. the alu executes the instructions. the cpu registers contain data, addresses, and status bits that reflect the results of cpu operations. see figure 3-1 . features include: 2.1-mhz bus frequency 8-bit accumulator 8-bit index register 11-bit program counter 6-bit stack pointer condition code register (ccr) with five status flags 62 instructions eight addressing modes power-saving stop, wait, halt, and data-retention modes 3.3 cpu control unit the cpu control unit fetches and decodes instructions during program operation. the control unit selects the memory locations to read and write and coordinates the timing of all cpu operations. 3.4 arithmetic/logic unit the arithmetic/logic unit (alu) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the cpu control unit. the alu produces the results called for by the program and sets or clears status and control bits in the condition code register (ccr).
central processor unit (cpu) arithmetic/logic unit mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 47 figure 3-1. programming model accumulator (a) index register (x) condition code register (ccr) program counter (pc) stack pointer (sp) half-carry flag interrupt mask negative flag zero flag carry/borrow flag 0 4 75 6 321 0 arithmetic/logic unit cpu control unit 0 4 75 6 321 0 4 75 6 321 8 12 15 13 14 11 10 9 000000011 0 00 0 4 75 6 321 8 12 15 13 14 11 10 9 111hinzc 0 4 75 6 321 0 0
technical data mc68hc705j1a ? rev. 4.0 48 central processor unit (cpu) motorola central processor unit (cpu) 3.5 cpu registers the m68hc05 cpu contains five registers that control and monitor microcontroller unit (mcu) operation: accumulator index register stack pointer program counter condition code register cpu registers are not memory mapped. 3.5.1 accumulator the accumulator (a) is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of alu operations. 3.5.2 index register in the indexed addressing (x) modes, the cpu uses the byte in the index register to determine the conditional address of the operand. the index register also can serve as a temporary storage location or a counter. bit 7654321bit 0 read: write: reset: unaffected by reset figure 3-2. accumulator (a) bit 7654321bit 0 read: write: reset: unaffected by reset figure 3-3. index register (x)
central processor unit (cpu) cpu registers mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 49 3.5.3 stack pointer the stack pointer (sp) is a 16-bit register that contains the address of the next location on the stack. during a reset or after the reset stack pointer instruction (rsp), the stack pointer is preset to $00ff. the address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked. the 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations; an interrupt uses five locations. bit 151413121110987654321 bit 0 read:0000000011 write: reset:0000000011111111 = unimplemented figure 3-4. stack pointer (sp)
technical data mc68hc705j1a ? rev. 4.0 50 central processor unit (cpu) motorola central processor unit (cpu) 3.5.4 program counter the program counter (pc) is a 16-bit register that contains the address of the next instruction or operand to be fetched. the five most significant bits of the program counter are ignored and appear as 00000. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.5.5 condition code register the condition code register (ccr) is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. bit 151413121110987654321 bit 0 read: write: reset: 0 0 0 0 0 loaded with vector from $07fe and $07ff figure 3-5. program counter (pc) bit 7654321bit 0 read: 1 1 1 hinzc write: reset:111u1uuu = unimplemented u = unaffected figure 3-6. condition code register (ccr)
central processor unit (cpu) cpu registers mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 51 h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add (add without carry) or adc (add with carry) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. i ? interrupt mask bit setting the interrupt mask disables interrupts. if an interrupt request occurs while the interrupt mask is logic 0, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is logic 1, the interrupt request is latched. normally, the cpu processes the latched interrupt request as soon as the interrupt mask is cleared again. a return-from-interrupt instruction (rti) unstacks the cpu registers, restoring the interrupt mask to its cleared state. after any reset, the interrupt mask is set and can be cleared only by a software instruction. n ? negative flag the cpu sets the negative flag when an alu operation produces a negative result. z ? zero flag the cpu sets the zero flag when an alu operation produces a result of $00. c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag.
technical data mc68hc705j1a ? rev. 4.0 52 central processor unit (cpu) motorola central processor unit (cpu) 3.6 instruction set the mcu instruction set has 62 instructions and uses eight addressing modes. 3.6.1 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 3.6.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 3.6.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte.
central processor unit (cpu) instruction set mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 53 3.6.1.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 3.6.1.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 3.6.1.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000 ? $00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or input/output (i/o) location. 3.6.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000 ? $01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe).
technical data mc68hc705j1a ? rev. 4.0 54 central processor unit (cpu) motorola central processor unit (cpu) the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 3.6.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 3.6.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two ? s complement byte that gives a branching range of ? 128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch.
central processor unit (cpu) instruction set mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 55 3.6.2 instruction types the mcu instructions fall into these five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions 3.6.2.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 3-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
technical data mc68hc705j1a ? rev. 4.0 56 central processor unit (cpu) motorola central processor unit (cpu) 3.6.2.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write instructions on registers with write-only bits. table 3-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one ? s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two ? s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value.
central processor unit (cpu) instruction set mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 57 3.6.2.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ? 128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. note: do not use brclr or brset instructions on registers with write-only bits.
technical data mc68hc705j1a ? rev. 4.0 58 central processor unit (cpu) motorola central processor unit (cpu) table 3-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
central processor unit (cpu) instruction set mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 59 3.6.2.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. note: do not use bit manipulation instructions on registers with write-only bits. table 3-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset
technical data mc68hc705j1a ? rev. 4.0 60 central processor unit (cpu) motorola central processor unit (cpu) 3.6.2.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 3-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
central processor unit (cpu) instruction set summary mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 61 3.7 instruction set summary table 3-6. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr and opr and opr ,x and opr ,x and ,x logical and a (a) (m) ?? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 c b0 b7 0 b0 b7 c
technical data mc68hc705j1a ? rev. 4.0 62 central processor unit (cpu) motorola central processor unit (cpu) bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ?? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 table 3-6. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
central processor unit (cpu) instruction set summary mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 63 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0inh98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 01 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one ? s complement) m ( m ) = $ff ? (m) a ( a ) = $ff ? (a) x ( x ) = $ff ? (x) m ( m ) = $ff ? (m) m ( m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ?? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ?? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 table 3-6. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
technical data mc68hc705j1a ? rev. 4.0 64 central processor unit (cpu) motorola central processor unit (cpu) jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ?? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ?? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ?? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0inh42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ?? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 table 3-6. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) instruction set summary mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 65 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ????? inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1inh99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ?? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ??? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ?? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ?? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 3-6. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 b0 b7 c
technical data mc68hc705j1a ? rev. 4.0 66 central processor unit (cpu) motorola central processor unit (cpu) 3.8 opcode map see table 3-7 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 10 tax transfer accumulator to index register x (a) ????? inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ( ) negation (two ? s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 3-6. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
mc68hc705j1a ? rev. 4.0 technical data motorola central processor unit (cpu) 67 central processor unit (cpu) opcode map table 3-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789a bcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 tax 1inh 4 sta 2dir 5 sta 3ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
technical data mc68hc705j1a ? rev. 4.0 68 central processor unit (cpu) motorola central processor unit (cpu)
mc68hc705j1a ? rev. 4.0 technical data motorola resets and interrupts 69 technical data ? mc68hc705j1a section 4. resets and interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 4.3 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.3.3 cop watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 4.3.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.2 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.3 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.4.3.1 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.4.3.2 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . .76 4.4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.2 introduction reset initializes the microcontroller unit (mcu) by returning the program counter to a known address and by forcing control and status bits to known states. interrupts temporarily change the sequence of program execution to respond to events that occur during processing.
technical data mc68hc705j1a ? rev. 4.0 70 resets and interrupts motorola resets and interrupts 4.3 resets a reset immediately stops the operation of the instruction being executed, initializes certain control and status bits, and loads the program counter with a user-defined reset vector address. these sources can generate a reset: power-on reset (por) circuit reset pin computer operating properly (cop) watchdog illegal address figure 4-1. reset sources dq ck s reset latch internal clock rst to cpu and reset pin v dd peripheral modules illegal address cop watchdog power-on reset
resets and interrupts resets mc68hc705j1a ? rev. 4.0 technical data motorola resets and interrupts 71 4.3.1 power-on reset a positive transition on the v dd pin generates a power-on reset. note: the power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. a 4064-t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if any reset source is active at the end of this delay, the mcu remains in the reset condition until all reset sources are inactive. figure 4-2. power-on reset timing oscillator stabilization delay v dd osc1 pin internal clock internal address bus notes: internal data bus 1. power-on reset threshold is typically between 1 v and 2 v. 2. internal clock, internal address bus, and internal data bus are not available externally. $07fe $07fe $07fe $07fe $07fe $07fe $07ff new pch new pcl (note 1)
technical data mc68hc705j1a ? rev. 4.0 72 resets and interrupts motorola resets and interrupts 4.3.2 external reset a logic 0 applied to the reset pin for 1 1/2 t cyc generates an external reset. a schmitt trigger senses the logic level at the reset pin. figure 4-3. external reset timing 4.3.3 cop watchdog reset a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. to clear the cop watchdog and prevent a cop reset, write a logic 0 to bit 0 (copc) of the cop register at location $07f0. 4.3.4 illegal address reset an opcode fetch from an address not in random-access memory (ram) or erasable, programmable read-only memory (eprom) generates a reset. table 4-1. external reset timing characteristic symbol min max unit reset pulse width t rl 1.5 ? t cyc internal clock internal address bus notes: internal data bus $07fe $07fe $07fe $07fe $07ff new pc 1. internal clock, internal address bus, and internal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pc new pcl dummy op code reset
resets and interrupts interrupts mc68hc705j1a ? rev. 4.0 technical data motorola resets and interrupts 73 4.4 interrupts these sources can generate interrupts: software interrupt (swi) instruction external interrupt pins: ? irq /v pp ? pa0 ? pa3 timer: ? real-time interrupt flag (rtif) ? timer overflow flag (tof) an interrupt temporarily stops the program sequence to process a particular event. an interrupt does not stop the operation of the instruction being executed, but takes effect when the current instruction completes its execution. interrupt processing automatically saves the cpu registers on the stack and loads the program counter with a user-defined interrupt vector address. 4.4.1 software interrupt the software interrupt (swi) instruction causes a non-maskable interrupt. 4.4.2 external interrupt an interrupt signal on the irq /v pp pin latches an external interrupt request. when the cpu completes its current instruction, it tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register. if the i bit is clear, the cpu then begins the interrupt sequence.
technical data mc68hc705j1a ? rev. 4.0 74 resets and interrupts motorola resets and interrupts the cpu clears the irq latch during interrupt processing, so that another interrupt signal on the irq /v pp pin can latch another interrupt request during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 4-4 shows the irq /v pp pin interrupt logic. figure 4-4. external interrupt logic setting the i bit in the condition code register disables external interrupts. the port a external interrupt bit (pirq) in the mask option register enables pins pa0 ? pa3 to function as external interrupt pins. the external interrupt sensitivity bit (level) in the mask option register controls interrupt triggering sensitivity of external interrupt pins. the irq /v pp pin can be negative-edge triggered only or negative-edge and low-level triggered. port a external interrupt pins can be positive-edge triggered only or both positive-edge and high-level triggered. the level-sensitive triggering option allows multiple external interrupt sources to be wire-ored to an external interrupt pin. an external interrupt request, shown in figure 4-5 , is latched as long as any source is holding an external interrupt pin low. pirq level-sensitive trigger pa3 pa2 pa1 irq pa0 v dd (mor level bit) reset irq vector fetch external interrupt request (mor) to bih & bil instruction processing irqf irqr irqe dq ck irq clr latch
resets and interrupts interrupts mc68hc705j1a ? rev. 4.0 technical data motorola resets and interrupts 75 figure 4-5. external interrupt timing table 4-2. external interrupt timing (v dd = 5.0 vdc) (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted characteristic symbol min max unit interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil note (2) 2. the minimum, t ilil , should not be less than the number of interrupt service routine cycles plus 19 t cyc . ? t cyc table 4-3. external interrupt timing (v dd = 3.3 vdc) (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted characteristic symbol min max unit interrupt pulse width low (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil note (2) 2. the minimum, t ilil , should not be less than the number of interrupt service routine cycles plus 19 t cyc . ? t cyc irq (internal) t ilih t ilil t ilih irq pin irq 1 irq n . . .
technical data mc68hc705j1a ? rev. 4.0 76 resets and interrupts motorola resets and interrupts 4.4.3 timer interrupts the timer can generate these interrupt requests: real time timer overflow setting the i bit in the condition code register disables timer interrupts. 4.4.3.1 real-time interrupt a real-time interrupt occurs if the real-time interrupt flag, rtif, becomes set while the real-time interrupt enable bit, rtie, is also set. rtif and rtie are in the timer status and control register. 4.4.3.2 timer overflow interrupt a timer overflow interrupt request occurs if the timer overflow flag, tof, becomes set while the timer overflow interrupt enable bit, toie, is also set. tof and toie are in the timer status and control register. 4.4.4 interrupt processing the cpu takes these actions to begin servicing an interrupt: stores the cpu registers on the stack in the order shown in figure 4-6 sets the i bit in the condition code register to prevent further interrupts loads the program counter with the contents of the appropriate interrupt vector locations: ? $07fc and $07fd (software interrupt vector) ? $07fa and $07fb (external interrupt vector) ? $07f8 and $07f9 (timer interrupt vector) the return-from-interrupt (rti) instruction causes the cpu to recover the cpu registers from the stack as shown in figure 4-6 .
resets and interrupts interrupts mc68hc705j1a ? rev. 4.0 technical data motorola resets and interrupts 77 figure 4-6. interrupt stacking order table 4-4. reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on reset pin cop watchdog (1) illegal address 1. the cop watchdog is programmable in the mask option register. none none 1 $07fe ? $07ff software interrupt (swi) user code none none same priority as instruction $07fc ? $07fd external interrupt irq /v pp pin irqe i bit 2 $07fa ? $07fb timer interrupts rtif bit tof bit rtie bit toie bit i bit 3 $07f8 ? $07f9 condition code register $00c0 (bottom of stack) $00c1 $00c2 accumulator index register program counter (high byte) program counter (low byte) $00fd $00fe $00ff (top of stack) 1 2 3 4 5 5 4 3 2 1 unstacking order stacking order
technical data mc68hc705j1a ? rev. 4.0 78 resets and interrupts motorola resets and interrupts figure 4-7. interrupt flowchart external interrupt? i bit set? timer interrupt? fetch next instruction swi instruction? rti instruction? stack pc, x, a, ccr set i bit load pc with interrupt vector yes yes yes yes yes unstack ccr, a, x, pc execute instruction clear irq latch no no no no no from reset
mc68hc705j1a ? rev. 4.0 technical data motorola low-power modes 79 technical data ? mc68hc705j1a section 5. low-power modes 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.3 exiting stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . .80 5.4 effects of stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.2 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.4.3 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.4.4 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.4.5 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.4.6 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 introduction the microcontroller unit (mcu) can enter these low-power standby modes: stop mode ? the stop instruction puts the mcu in its lowest power-consumption mode. wait mode ? the wait instruction puts the mcu in an intermediate power-consumption mode. halt mode ? halt mode is identical to wait mode, except that an oscillator stabilization delay of 1 to 4064 internal clock cycles occurs when the mcu exits halt mode. the stop-to-wait conversion bit, swait, in the mask option register, enables halt mode.
technical data mc68hc705j1a ? rev. 4.0 80 low-power modes motorola low-power modes enabling halt mode prevents the computer operating properly (cop) watchdog from being inadvertently turned off by a stop instruction. data-retention mode ? in data-retention mode, the mcu retains ram contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low power-consumption state during which it retains data, but the cpu cannot execute instructions. 5.3 exiting stop and wait modes the events described in this subsection bring the mcu out of stop mode and load the program counter with the reset vector or with an interrupt vector. exiting stop mode: external reset ? a logic 0 on the reset pin resets the mcu, starts the cpu clock, and loads the program counter with the contents of locations $07fe and $07ff. external interrupt ? a high-to-low transition on the irq /v pp pin or a low-to-high transition on an enabled port a external interrupt pin starts the cpu clock and loads the program counter with the contents of locations $07fa and $07fb. exiting wait mode: external reset ? a logic 0 on the reset pin resets the mcu, starts the cpu clock, and loads the program counter with the contents of locations $07fe and $07ff. external interrupt ? a high-to-low transition on the irq /v pp pin or a low-to-high transition on an enabled port a external interrupt pin starts the cpu clock and loads the program counter with the contents of locations $07fa and $07fb.
low-power modes effects of stop and wait modes mc68hc705j1a ? rev. 4.0 technical data motorola low-power modes 81 cop watchdog reset ? a timeout of the cop watchdog resets the mcu, starts the cpu clock, and loads the program counter with the contents of locations $07fe and $07ff. software can enable timer interrupts so that the mcu periodically can exit wait mode to reset the cop watchdog. timer interrupt ? real-time interrupt requests and timer overflow interrupt requests start the mcu clock and load the program counter with the contents of locations $07f8 and $07f9. 5.4 effects of stop and wait modes the stop and wait instructions have the effects described in this subsection on mcu modules. 5.4.1 clock generation the stop instruction: the stop instruction disables the internal oscillator, stopping the cpu clock and all peripheral clocks. after exiting stop mode, the cpu clock and all enabled peripheral clocks begin running after the oscillator stabilization delay. note: the oscillator stabilization delay holds the mcu in reset for the first 4064 internal clock cycles. the wait instruction: the wait instruction disables the cpu clock. after exiting wait mode, the cpu clock and all enabled peripheral clocks immediately begin running.
technical data mc68hc705j1a ? rev. 4.0 82 low-power modes motorola low-power modes 5.4.2 cpu the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. after exit from stop mode by external interrupt, the i bit remains clear. after exit from stop mode by reset, the i bit is set. the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts disables the cpu clock after exit from wait mode by interrupt, the i bit remains clear. after exit from wait mode by reset, the i bit is set. 5.4.3 cop watchdog the stop instruction: clears the cop watchdog counter disables the cop watchdog clock note: to prevent the stop instruction from disabling the cop watchdog, program the stop-to-wait conversion bit (swait) in the mask option register to logic 1. after exit from stop mode by external interrupt, the cop watchdog counter immediately begins counting from $0000 and continues counting throughout the oscillator stabilization delay. note: immediately after exiting stop mode by external interrupt, service the cop to ensure a full cop timeout period.
low-power modes effects of stop and wait modes mc68hc705j1a ? rev. 4.0 technical data motorola low-power modes 83 after exit from stop mode by reset: the cop watchdog counter immediately begins counting from $0000. the cop watchdog counter is cleared at the end of the oscillator stabilization delay and begins counting from $0000 again. the wait instruction: the wait instruction has no effect on the cop watchdog. note: to prevent a cop timeout during wait mode, exit wait mode periodically to service the cop. 5.4.4 timer the stop instruction: clears the rtie, tofe, rtif, and tof bits in the timer status and control register, disabling timer interrupt requests and removing any pending timer interrupt requests disables the clock to the timer after exiting stop mode by external interrupt, the timer immediately resumes counting from the last value before the stop instruction and continues counting throughout the oscillator stabilization delay. after exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation from its reset state. the wait instruction: the wait instruction has no effect on the timer.
technical data mc68hc705j1a ? rev. 4.0 84 low-power modes motorola low-power modes 5.4.5 eprom/otprom the stop instruction: the stop instruction during erasable, programmable read-only memory (eprom) programming clears the epgm bit in the eprom programming register, removing the programming voltage from the eprom. the wait instruction: the wait instruction has no effect on eprom/one-time programmable read-only memory (otprom) operation. 5.4.6 data-retention mode in data-retention mode, the mcu retains random-access memory (ram) contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low power-consumption state during which it retains data, but the cpu cannot execute instructions. to put the mcu in data-retention mode: 1. drive the reset pin to logic 0. 2. lower the v dd voltage. the reset pin must remain low continuously during data-retention mode. to take the mcu out of data-retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to logic 1.
low-power modes timing mc68hc705j1a ? rev. 4.0 technical data motorola low-power modes 85 5.5 timing figure 5-1. stop mode recovery timing t ilih oscillator stabilization delay osc t rl reset irq /v pp irq /v pp internal clock internal address notes: 1. internal clocking from osc1 pin 2. edge-triggered external interrupt mask option 3. edge- and level-triggered external interrupt mask option 4. reset vector shown as example reset or interrupt vector fetch $07fe $07fe $07fe $07fe $07fe $07ff (note 4) bus (note 3) (note 2) (note 1)
technical data mc68hc705j1a ? rev. 4.0 86 low-power modes motorola low-power modes figure 5-2. stop/halt/wait flowchart stop swait bit set? clear i bit in ccr set irqe bit in iscr clear tof, rtif, toie, and rtie bits in tscr turn off internal oscillator external reset? external interrupt? no no no turn on internal oscillator reset stabilization timer yes yes halt yes end of stabilization delay? yes no yes no no no cop reset? timer interrupt? external interrupt? external reset? clear i bit in ccr set irqe bit in iscr turn off cpu clock timer clock active yes yes yes yes no no no clear i bit in ccr set irqe bit in iscr turn off cpu clock timer clock active yes yes yes no no turn on cpu clock 1. load pc with reset vector or 2. service interrupt a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector external reset? wait external interrupt? timer interrupt? cop reset?
mc68hc705j1a ? rev. 4.0 technical data motorola parallel input/output (i/o) ports 87 technical data ? mc68hc705j1a section 6. parallel input/output (i/o) ports 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 6.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.3 pulldown register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6.3.4 port a led drive capability . . . . . . . . . . . . . . . . . . . . . . . . .92 6.3.5 port a i/o pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 6.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 6.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.4.3 pulldown register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 6.5 5.0-volt i/o port electrical characteristics . . . . . . . . . . . . . . . . 95 6.6 3.3-volt i/o port electrical characteristics . . . . . . . . . . . . . . . . 95 6.2 introduction fourteen bidirectional pins form one 8-bit input/output (i/o) port and one 6-bit i/o port. all the bidirectional port pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss. although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
technical data mc68hc705j1a ? rev. 4.0 88 parallel input/output (i/o) ports motorola parallel input/output (i/o) ports addr.register name bit 7654321bit 0 $0000 port a data register (porta) see page 89. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 92. read: 0 0 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 90. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 93. read: 0 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0010 pulldown register a (pdra) see page 91. read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 $0011 pulldown register b (pdrb) see page 94. read: write: pdib5 pdib4 pdib3 pdib2 pdib1 pdib0 reset: 000000 = unimplemented figure 6-1. parallel i/o port register summary
parallel input/output (i/o) ports port a mc68hc705j1a ? rev. 4.0 technical data motorola parallel input/output (i/o) ports 89 6.3 port a port a is an 8-bit bidirectional port. 6.3.1 port a data register the port a data register (porta) contains a latch for each port a pin. pa[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 6-2. port a data register (porta)
technical data mc68hc705j1a ? rev. 4.0 90 parallel input/output (i/o) ports motorola parallel input/output (i/o) ports 6.3.2 data direction register a data direction register a (ddra) determines whether each port a pin is an input or an output. ddra[7:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 6-4 shows the i/o logic of port a. figure 6-4. port a i/o circuitry address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 6-3. data direction register a (ddra) read ddra write ddra reset write porta read porta pax internal data bus ddrax pax pdrax swpdi 100- a pulldown (pa0 ? pa3 to irq module) write pdra 10-ma sink capability (pins pa4 ? pa7 only)
parallel input/output (i/o) ports port a mc68hc705j1a ? rev. 4.0 technical data motorola parallel input/output (i/o) ports 91 writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. when bit ddrax is a logic 1, reading address $0000 reads the pax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 6-1 summarizes the operation of the port a pins. 6.3.3 pulldown register a pulldown register a (pdra) inhibits the pulldown devices on port a pins programmed as inputs. note: if the swpdi bit in the mask option register is programmed to logic 1, reset initializes all port a pins as inputs with disabled pulldown devices. pdia[7:0] ? pulldown inhibit a bits pdia[7:0] disable the port a pulldown devices. reset clears pdia[7:0]. 1 = corresponding port a pulldown device disabled 0 = corresponding port a pulldown device not disabled table 6-1. port a pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, high-impedance pin latch (1) 1. writing affects the data register but does not affect input. 1 output latch latch address: $0010 bit 7654321bit 0 read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 = unimplemented figure 6-5. pulldown register a (pdra)
technical data mc68hc705j1a ? rev. 4.0 92 parallel input/output (i/o) ports motorola parallel input/output (i/o) ports 6.3.4 port a led drive capability the outputs for the upper four bits of port a (pa4 ? pa7) can drive light-emitting diodes (leds). pa4 ? pa7 can sink approximately 10 ma of current to v ss . 6.3.5 port a i/o pin interrupts if the pirq bit in the mask option register is programmed to logic 1, pa0 ? pa3 pins function as external interrupt pins. see section 8. external interrupt module (irq) . 6.4 port b port b is a 6-bit bidirectional port. 6.4.1 port b data register the port b data register (portb) contains a latch for each port b pin. pb[5:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. address: $0001 bit 7654321bit 0 read: 0 0 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset = unimplemented figure 6-6. port b data register (portb)
parallel input/output (i/o) ports port b mc68hc705j1a ? rev. 4.0 technical data motorola parallel input/output (i/o) ports 93 6.4.2 data direction register b data direction register b (ddrb) determines whether each port b pin is an input or an output. ddrb[5:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[5:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 6-8 shows the i/o logic of port b. figure 6-8. port b i/o circuitry address: $0005 bit 7654321bit 0 read: 0 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 6-7. data direction register b (ddrb) read ddrb write ddrb reset write portb read portb pbx internal data bus ddrbx pbx pdrbx swpdi 100- a pulldown write pdrb
technical data mc68hc705j1a ? rev. 4.0 94 parallel input/output (i/o) ports motorola parallel input/output (i/o) ports writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. when bit ddrbx is a logic 1, reading address $0001 reads the pbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 6-2 summarizes the operation of the port b pins. 6.4.3 pulldown register b pulldown register b (pdrb) inhibits the pulldown devices on port b pins programmed as inputs. note: if the swpdi bit in the mask option register is programmed to logic 1, reset initializes all port b pins as inputs with disabled pulldown devices. pdib[7:0] ? pulldown inhibit b bits pdib[7:0] disable the port b pulldown devices. reset clears pdib[7:0]. 1 = corresponding port b pulldown device disabled 0 = corresponding port b pulldown device not disabled table 6-2. port b pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, high-impedance pin latch (1) 1. writing affects the data register, but does not affect input. 1 output latch latch address: $0011 bit 7654321bit 0 read: write: pdib5 pdib4 pdib3 pdib2 pdib1 pdib0 reset: 000000 = unimplemented figure 6-9. pulldown register b (pdrb)
parallel input/output (i/o) ports 5.0-volt i/o port electrical characteristics mc68hc705j1a ? rev. 4.0 technical data motorola parallel input/output (i/o) ports 95 6.5 5.0-volt i/o port electrical characteristics 6.6 3.3-volt i/o port electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25 c. max unit current drain per pin excluding pa4 ? pa7 i ? 25 ? ma output high voltage (i load = ? 0.8 ma) pa0 ? pa7, pb0 ? pb5 v oh v dd ? 0.8 ?? v output low voltage (i load = 1.6 ma) pa0 ? pa3, pb0 ? pb5 (i load = 10.0 ma) pa4 ? pa7 v ol ? ? ? ? 0.4 0.4 v input high voltage pa0 ? pa7, pb0 ? pb5 v ih 0.7 x v dd ? v dd v input low voltage pa0 ? pa7, pb0 ? pb5 v il v ss ? 0.2 x v dd v i/o ports hi-z leakage current pa0 ? pa7, pb0 ? pb5 (without individual pulldown activated) i il ? 0.2 1 a input pulldown current pa0 ? pa7, pb0 ? pb5 (with individual pulldown activated) i il 35 80 200 a characteristic (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25 c. max unit current drain per pin excluding pa4 ? pa7 i ? 25 ? ma output high voltage (i load = ? 0.2 ma) pa0 ? pa7, pb0 ? pb5 v oh v dd ? 0.3 ?? v output low voltage (i load = 0.4 ma) pa0 ? pa3, pb0 ? pb5 (i load = 5.0 ma) pa4 ? pa7 v ol ? ? ? ? 0.3 0.3 v input high voltage pa0 ? pa7, pb0 ? pb5 v ih 0.7 x v dd ? v dd v input low voltage pa0 ? pa7, pb0 ? pb5 v il v ss ? 0.2 x v dd v i/o ports hi-z leakage current pa0 ? pa7, pb0 ? pb5 (without individual pulldown activated) i il ? 0.1 1 a input pulldown current pa0 ? pa7, pb0 ? pb5 (with individual pulldown activated) i il 12 30 100 a
technical data mc68hc705j1a ? rev. 4.0 96 parallel input/output (i/o) ports motorola parallel input/output (i/o) ports
mc68hc705j1a ? rev. 4.0 technical data motorola computer operating properly (cop) module 97 technical data ? mc68hc705j1a section 7. computer operating properly (cop) module 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.3.1 cop watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.3.2 cop watchdog timeout period . . . . . . . . . . . . . . . . . . . . . .98 7.3.3 clearing the cop watchdog . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.5 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.2 introduction the computer operating properly (cop) watchdog resets the microcontroller (mcu) in case of software failure. software that is operating properly periodically services the cop watchdog and prevents cop reset. the cop watchdog function is programmable by the copen bit in the mask option register. features include: protection from runaway software wait and halt mode operation
technical data mc68hc705j1a ? rev. 4.0 98 computer operating properly (cop) module motorola computer operating properly (cop) module 7.3 operation operation of the cop is described in this subsection. 7.3.1 cop watchdog timeout four counter stages at the end of the timer make up the cop watchdog. the cop resets the mcu if the timeout period occurs before the cop watchdog timer is cleared by application software and the irq /v pp pin voltage is between v ss and v dd . periodically clearing the counter starts a new timeout period and prevents cop reset. a cop watchdog timeout indicates that the software is not executing instructions in the correct sequence. note: the internal clock drives the cop watchdog. therefore, the cop watchdog cannot generate a reset for errors that cause the internal clock to stop. the cop watchdog depends on a power supply voltage at or above a minimum specification and is not guaranteed to protect against brownout. 7.3.2 cop watchdog timeout period the cop watchdog timer function is implemented by dividing the output of the real-time interrupt circuit (rti) by eight. the rti select bits in the timer status and control register control rti output, and the selected output drives the cop watchdog. see timer status and control register in section 9. multifunction timer module . note: the minimum cop timeout period is seven times the rti period. the cop is cleared asynchronously with the value in the rti divider; hence, the cop timeout period will vary between 7x and 8x the rti period. 7.3.3 clearing the cop watchdog to clear the cop watchdog and prevent a cop reset, write a logic 0 to bit 0 (copc) of the cop register at location $07f0 (see figure 7-1 ).
computer operating properly (cop) module interrupts mc68hc705j1a ? rev. 4.0 technical data motorola computer operating properly (cop) module 99 clearing the cop bit disables the cop watchdog timer regardless of the irq /v pp pin voltage. if the main program executes within the cop timeout period, the clearing routine should be executed only once. if the main program takes longer than the cop timeout period, the clearing routine must be executed more than once. note: place the clearing routine in the main program and not in an interrupt routine. clearing the cop watchdog in an interrupt routine might prevent cop watchdog timeouts even though the main program is not operating properly. 7.4 interrupts the cop watchdog does not generate interrupts. 7.5 cop register the cop register (copr) is a write-only register that returns the contents of eprom location $07f0 when read. copc ? cop clear bit this write-only bit resets the cop watchdog. reading address $07f0 returns undefined results. address: $07f0 bit 7654321bit 0 read: write: copc reset: 0 = unimplemented figure 7-1. cop register (copr)
technical data mc68hc705j1a ? rev. 4.0 100 computer operating properly (cop) module motorola computer operating properly (cop) module 7.6 low-power modes the stop and wait instructions have these effects on the cop watchdog. 7.6.1 stop mode the stop instruction clears the cop watchdog counter and disables the clock to the cop watchdog. note: to prevent the stop instruction from disabling the cop watchdog, program the stop-to-wait conversion bit (swait) in the mask option register to logic 1. upon exit from stop mode by external reset: the counter begins counting from $0000. the counter is cleared again after the oscillator stabilization delay and begins counting from $0000 again. upon exit from stop mode by external interrupt: the counter begins counting from $0000. the counter is not cleared again after the oscillator stabilization delay and continues counting throughout the oscillator stabilization delay. note: immediately after exiting stop mode by external interrupt, service the cop to ensure a full cop timeout period. 7.6.2 wait mode the wait instruction has no effect on the cop watchdog. note: to prevent a cop timeout during wait mode, exit wait mode periodically to service the cop.
mc68hc705j1a ? rev. 4.0 technical data motorola external interrupt module (irq) 101 technical data ? mc68hc705j1a section 8. external interrupt module (irq) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8.3.1 irq /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 8.3.2 optional external interrupts . . . . . . . . . . . . . . . . . . . . . . . .104 8.4 irq status and control register . . . . . . . . . . . . . . . . . . . . . .106 8.5 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.5.1 5.0-volt external interrupt timing characteristics . . . . . . .107 8.5.2 3.3-volt external interrupt timing characteristics . . . . . . .107 8.2 introduction the external interrupt (irq) module provides asynchronous external interrupts to the cpu. these sources can generate external interrupts: irq /v pp pin pa0 ? pa3 pins features include: dedicated external interrupt pin (irq /v pp ) selectable interrupt on four input/output (i/o) pins (pa0 ? pa3) programmable edge-only or edge- and level-interrupt sensitivity
technical data mc68hc705j1a ? rev. 4.0 102 external interrupt module (irq) motorola external interrupt module (irq) 8.3 operation the interrupt request/programming voltage pin (irq /v pp ) and port a pins 0 ? 3 (pa0 ? pa3) provide external interrupts. the pirq bit in the mask option register (mor) enables pa0 ? pa3 as irq interrupt sources, which are combined into a single oring function to be latched by the irq latch. figure 8-1 shows the structure of the irq module. after completing its current instruction, the cpu tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register and the irqe bit in the irq status and control register. if the i bit is clear and the irqe bit is set, the cpu then begins the interrupt sequence. this interrupt is serviced by the interrupt service routine located at $07fa and $07fb. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 8-2 shows the sequence of events caused by an interrupt. figure 8-1. irq module block diagram pirq level-sensitive trigger pa3 pa2 pa1 irq pa0 v dd (mor level bit) reset irq vector fetch external interrupt request (mor) to bih & bil instruction processing irqf irqr irqe dq ck irq clr latch
external interrupt module (irq) operation mc68hc705j1a ? rev. 4.0 technical data motorola external interrupt module (irq) 103 figure 8-2. interrupt flowchart external interrupt? i bit set? timer interrupt? fetch next instruction swi instruction? rti instruction? stack pcl, pch, x, a, ccr set i bit load pc with interrupt vector yes yes yes yes yes unstack ccr, a, x, pch, pcl execute instruction clear irq latch no no no no no from reset
technical data mc68hc705j1a ? rev. 4.0 104 external interrupt module (irq) motorola external interrupt module (irq) 8.3.1 irq /v pp pin an interrupt signal on the irq /v pp pin latches an external interrupt request. the level bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. if edge- and level-sensitive triggering is selected, a falling edge or a low level on the irq /v pp pin latches an external interrupt request. edge- and level-sensitive triggering allows the use of multiple wired-or external interrupt sources. an external interrupt request is latched as long as any source is holding the irq /v pp pin low. if level-sensitive triggering is selected, the irq /v pp input requires an external resistor to v dd for wired-or operation. if the irq /v pp pin is not used, it must be tied to the v dd supply. if edge-sensitive-only triggering is selected, a falling edge on the irq /v pp pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level on the irq /v pp pin returns to logic 1 and then falls again to logic 0. the irq /v pp pin contains an internal schmitt trigger as part of its input to improve noise immunity. the voltage on this pin can affect the mode of operation and should not exceed v dd . 8.3.2 optional external interrupts the inputs for the lower four bits of port a (pa0 ? pa3) can be connected to the irq pin input of the cpu if enabled by the pirq bit in the mask option register. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq /v pp pin except for the inverted phase (logic 1, rising edge). the active state of the irq /v pp pin is a logic 0 (falling edge). the pa0 ? pa3 pins are selected as a group to function as irq interrupts and are enabled by the irqe bit in the irq status and control register. the pa0 ? pa3 pins can be positive-edge triggered only or positive-edge and high-level triggered.
external interrupt module (irq) operation mc68hc705j1a ? rev. 4.0 technical data motorola external interrupt module (irq) 105 if edge- and level-sensitive triggering is selected, a rising edge or a high level on a pa0 ? pa3 pin latches an external interrupt request. edge- and level-sensitive triggering allows the use of multiple wired-or external interrupt sources. as long as any source is holding a pa0 ? pa3 pin high, an external interrupt request is latched, and the cpu continues to execute the interrupt service routine. if edge-sensitive only triggering is selected, a rising edge on a pa0 ? pa3 pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to logic 0 and then rises again to logic 1. note: the branch if interrupt pin is high (bih) and branch if interrupt pin is low (bil) instructions apply only to the level on the irq /v pp pin itself and not to the output of the logic or function with the pa0 ? pa3 pins. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. enabled pa0 ? pa3 pins cause an irq interrupt regardless of whether these pins are configured as inputs or outputs. the irq pin has an internal schmitt trigger. the optional external interrupts (pa0 ? pa3) do not have internal schmitt triggers. the interrupt mask bit (i) in the condition code register (ccr) disables all maskable interrupt requests, including external interrupt requests.
technical data mc68hc705j1a ? rev. 4.0 106 external interrupt module (irq) motorola external interrupt module (irq) 8.4 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. all unused bits in the iscr read as logic 0s. the irqf bit is cleared and the irqe bit is set by reset. irqr ? interrupt request reset bit this write-only bit clears the external interrupt request flag. 1 = clears external interrupt and irqf bit 0 = no effect on external interrupt and irqf bit irqf ? external interrupt request flag the external interrupt request flag is a clearable, read-only bit that is set when an external interrupt request is pending. reset clears the irqf bit. 1 = external interrupt request pending 0 = no external interrupt request pending irqe ? external interrupt request enable bit this read/write bit enables external interrupts. reset sets the irqe bit. 1 = external interrupt requests enabled 0 = external interrupt requests disabled the stop and wait instructions set the irqe bit so that an external interrupt can bring the mcu out of these low-power modes. in addition, reset sets the i bit which masks all interrupt sources. address: $000a bit 7654321bit 0 read: irqe 000irqf000 write: r irqr reset:10000000 = unimplemented r = reserved figure 8-3. irq status and control register (iscr)
external interrupt module (irq) external interrupt timing mc68hc705j1a ? rev. 4.0 technical data motorola external interrupt module (irq) 107 8.5 external interrupt timing figure 8-4. external interrupt timing 8.5.1 5.0-volt external interrupt timing characteristics 8.5.2 3.3-volt external interrupt timing characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c , unless otherwise noted symbol min max unit irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc (2) 2. t cyc = 1/f op ; f op = f osc /2. irq interrupt pulse width (edge- and level-triggered) t ilih 1.5 note (3) 3. the minimum, t ilil , should not be less than the number of interrupt service routine cycles plus 19 t cyc . t cyc pa0 ? pa3 interrupt pulse width high (edge-triggered) t ilil 1.5 ? t cyc pa0 ? pa3 interrupt pulse width high (edge- and level-triggered) t ilih 1.5 note (3) t cyc characteristic (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min max unit irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc (2) 2. t cyc = 1/f op ; f op = f osc /2. irq interrupt pulse width (edge- and level-triggered) t ilih 1.5 note (3) 3. the minimum, t ilil , should not be less than the number of interrupt service routine cycles plus 19 t cyc . t cyc pa0 ? pa3 interrupt pulse width high (edge-triggered) t ilil 1.5 ? t cyc pa0 ? pa3 interrupt pulse width high (edge- and level-triggered) t ilih 1.5 note (3) t cyc irq (internal) t ilih t ilil t ilih irq pin irq 1 irq n . . .
technical data mc68hc705j1a ? rev. 4.0 108 external interrupt module (irq) motorola external interrupt module (irq)
mc68hc705j1a ? rev. 4.0 technical data motorola multifunction timer module 109 technical data ? mc68hc705j1a section 9. multifunction timer module 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 9.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 9.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.5 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.5.1 timer status and control register . . . . . . . . . . . . . . . . . . .112 9.5.2 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.2 introduction the multifunction timer provides a timing reference with programmable real-time interrupt (rti) capability. figure 9-1 shows the timer organization. features include: timer overflow four selectable interrupt rates computer operating properly (cop) watchdog timer
technical data mc68hc705j1a ? rev. 4.0 110 multifunction timer module motorola multifunction timer module figure 9-1. multifunction timer block diagram clear cop timer timer counter register bits [0:7] of 15-stage overflow 4 internal clock (xtal 2) timer status/control register tof rtif toie rtie tofr rtifr rt1 rt0 rti rate select 2 2 2 2 2 2 2 bits [8:14] of 15-stage ripple counter 8 s r q interrupt request cop reset internal data bus reset ripple counter reset reset reset
multifunction timer module operation mc68hc705j1a ? rev. 4.0 technical data motorola multifunction timer module 111 9.3 operation a 15-stage ripple counter, preceded by a prescaler that divides the internal clock signal by four, provides the timing reference for the timer functions. the value of the first eight timer stages can be read at any time by accessing the timer counter register at address $0009. a timer overflow function at the eighth stage allows a timer interrupt every 1024 internal clock cycles. the next four stages lead to the real-time interrupt (rti) circuit. the rt1 and rt0 bits in the timer status and control register at address $0008 allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock cycles. the last four stages drive the selectable cop system. for information on the cop, refer to the section 7. computer operating properly (cop) module . addr.register name bit 7654321bit 0 $0008 timer status and control register (tscr) see page 112. read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 $0009 timer counter register (tcr) see page 114. read: tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 write: reset:00000000 = unimplemented figure 9-2. i/o register summary
technical data mc68hc705j1a ? rev. 4.0 112 multifunction timer module motorola multifunction timer module 9.4 interrupts these timer sources can generate interrupts: timer overflow flag (tof) ? the tof bit is set when the first eight stages of the counter roll over from $ff to $00. the timer overflow interrupt enable bit, toie, enables tof interrupt requests. real-time interrupt flag (rtif) ? the rtif bit is set when the selected rti output becomes active. the real-time interrupt enable bit, rtie, enables rtif interrupt requests. 9.5 i/o registers these registers control and monitor the timer operation: timer status and control register (tscr) timer counter register (tcr) 9.5.1 timer status and control register the read/write timer status and control register (tscr) performs these functions: flags timer interrupts enables timer interrupts resets timer interrupt flags selects real-time interrupt rates address: $0008 bit 7654321bit 0 read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 = unimplemented figure 9-3. timer status and control register (tscr)
multifunction timer module i/o registers mc68hc705j1a ? rev. 4.0 technical data motorola multifunction timer module 113 tof ? timer overflow flag this read-only flag becomes set when the first eight stages of the counter roll over from $ff to $00. tof generates a timer overflow interrupt request if toie is also set. clear tof by writing a logic 1 to the tofr bit. writing to tof has no effect. reset clears tof. rtif ? real-time interrupt flag this read-only flag becomes set when the selected rti output becomes active. rtif generates a real-time interrupt request if rtie is also set. clear rtif by writing a logic 1 to the rtifr bit. writing to rtif has no effect. reset clears rtif. toie ? timer overflow interrupt enable bit this read/write bit enables timer overflow interrupts. reset clears toie. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled rtie ? real-time interrupt enable bit this read/write bit enables real-time interrupts. reset clears rtie. 1 = real-time interrupts enabled 0 = real-time interrupts disabled tofr ? timer overflow flag reset bit writing a logic 1 to this write-only bit clears the tof bit. tofr always reads as logic 0. reset clears tofr. rtifr ? real-time interrupt flag reset bit writing a logic 1 to this write-only bit clears the rtif bit. rtifr always reads as logic 0. reset clears rtifr. rt1 and rt0 ? real-time interrupt select bits these read/write bits select one of four real-time interrupt rates, as shown in table 9-1 . because the selected rti output drives the cop watchdog, changing the real-time interrupt rate also changes the counting rate of the cop watchdog. reset sets rt1 and rt0. note: changing rt1 and rt0 when a cop timeout is imminent can cause a real-time interrupt request to be missed or an additional real-time
technical data mc68hc705j1a ? rev. 4.0 114 multifunction timer module motorola multifunction timer module interrupt request to be generated. to prevent this occurrence, clear the cop timer before changing rt1 and rt0. 9.5.2 timer counter register a 15-stage ripple counter is the core of the timer. the value of the first eight stages is readable at any time from the read-only timer counter register (tcr) shown in figure 9-4 . power-on clears the entire counter chain and the internal clock begins clocking the counter. after 4064 cycles (or 16 cycles if the soscd bit in the mask option register is set), the power-on reset circuit is released, clearing the counter again and allowing the mcu to come out of reset. a timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles. table 9-1. real-time interrupt rate selection rt1:rt0 number of cycles to rti rti period (1) 1. at 2-mhz bus, 4-mhz xtal, 0.5 s per cycle number of cycles to cop reset cop timeout period (1) 0 0 2 14 = 16,384 8.2 ms 2 17 = 131,072 65.5 ms 0 1 2 15 = 32,768 16.4 ms 2 18 = 262,144 131.1 ms 1 0 2 16 = 65,536 32.8 ms 2 19 = 524,288 262.1 ms 1 1 2 17 = 131,072 65.5 ms 2 20 = 1,048,576 524.3 ms address: $0009 bit 7654321bit 0 read: tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 write: reset:00000000 = unimplemented figure 9-4. timer counter register (tcr)
multifunction timer module low-power modes mc68hc705j1a ? rev. 4.0 technical data motorola multifunction timer module 115 9.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby states. 9.6.1 stop mode the stop instruction has these effects on the timer: clears the timer counter clears interrupt flags (tof and rtif) and interrupt enable bits (tofe and rtie) in tscr, removing any pending timer interrupt requests and disabling further timer interrupts. 9.6.2 wait mode the timer remains active after a wait instruction. any enabled timer interrupt request can bring the mcu out of wait mode.
technical data mc68hc705j1a ? rev. 4.0 116 multifunction timer module motorola multifunction timer module
mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 117 technical data ? mc68hc705j1a section 10. electrical specifications 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 10.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .119 10.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 10.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 10.7 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .121 10.8 3.3-volt dc electrical characteristics . . . . . . . . . . . . . . . . . . 122 10.9 driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.10 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.11 eprom programming characteristics . . . . . . . . . . . . . . . . . .126 10.12 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 10.13 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 10.2 introduction this section contains electrical and timing specifications.
technical data mc68hc705j1a ? rev. 4.0 118 electrical specifications motorola electrical specifications 10.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 10.7 5.0-volt dc electrical characteristics and 10.8 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating (1) 1. voltages are referenced to v ss . symbol value unit supply voltage v dd ? 0.3 to +7.0 v current drain per pin (excluding v dd , v ss , and pa4 ? pa7) i25ma input voltage v in v ss ? 0.3 to v dd + 0.3 v irq /v pp pin v pp v ss ? 0.3 to 2 x v dd + 0.3 v storage temperature range t stg ? 65 to +150 c
electrical specifications operating temperature range mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 119 10.4 operating temperature range 10.5 thermal characteristics package type symbol value (t l to t h ) unit mc68hc705j1ap (1) , dw (2) , s (3) 1. p = plastic dual in-line package (pdip) 2. dw = small outline integrated circuit (soic) 3. s = ceramic dip (cerdip) t a 0 to 70 c mc68hc705j1ac (4) p, cdw, cs 4. c = extended temperature range t a ? 40 to +85 c mc68hc705j1av (5) p, vdw, vs 5. v = automotive temperature range t a ? 40 to +105 c characteristic symbol value unit thermal resistance mc68hc705j1ap (1) mc68hc705j1adw (2) mc68hc705j1as (3) 1. p = plastic dual in-line package (pdip) 2. dw = small outline integrated circuit (soic) 3. s = ceramic dip (cerdip) ja 60 c/w
technical data mc68hc705j1a ? rev. 4.0 120 electrical specifications motorola electrical specifications 10.6 power considerations the average chip junction temperature, t j , in c can be obtained from: t j = t a + (p d x ja )(1) where: t a = ambient temperature in c ja = package thermal resistance, junction to ambient in c/w p d = p int + p i/o p int = i cc v cc = chip internal power dissipation p i/o = power dissipation on input and output pins (user-determined) for most applications, p i/o < p int and can be neglected. ignoring p i/o , the relationship between p d and t j is approximately: (2) solving equations (1) and (2) for k gives: = p d x (t a + 273 c) + ja x (p d ) 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . p d = t j + 273 c k
electrical specifications 5.0-volt dc electrical characteristics mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 121 10.7 5.0-volt dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min typ (2) 2. typical values at midpoint of voltage range, 25 c only max unit output voltage i load = 10.0 a i load = ? 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i load = ? 0.8 ma) pa0 ? pa7, pb0 ? pb5 v oh v dd ? 0.8 ?? v output low voltage (i load = 1.6 ma) pa0 ? pa3, pb0 ? pb5 (i load = 10.0 ma) pa4 ? pa7 v ol ?? 0.4 0.4 v input high voltage pa0 ? pa7, pb0 ? pb5, irq /v pp , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa0 ? pa7, pb0 ? pb5, irq /v pp , reset , osc1 v il v ss ? 0.2 v dd v supply current run mode (3) wait mode (4) stop mode (5) 25 c ? 40 to 105 c 3. run mode i dd is measured using external square wave clock source (f osc = 4.2 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 4. wait mode i dd : only timer system active. wait mode is affected linearly by osc2 capacitance. wait mode is measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v. wait mode i dd is measured using external square wave clock source (f osc = 4.2 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 5. stop mode i dd is measured with osc1 = v ss . stop mode i dd is measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v i dd ? ? ? ? 3.5 0.45 0.2 2.0 6.0 2.75 10 20 ma ma a a i/o ports hi-z leakage current pa0 ? pa7, pb0 ? pb5 (without individual pulldown activated) i il ? 0.2 1 a input pulldown current pa0 ? pa7, pb0 ? pb5 (with individual pulldown activated) i il 35 80 200 a input pullup current reset i il ? 15 ? 35 ? 85 a input current (6) reset , irq /v pp , osc1 6. only input high current rated to +1 a on reset . i in ? 0.2 1 a capacitance ports (as inputs or outputs) reset , irq /v pp , osc1, osc2 c out c in ? ? ? ? 12 8 pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2 (7) 7. the r osc value selected for rc oscillator versions of this device is unspecified. see appendix c. mc68hsr705j1a for additional information. r osc 1.0 2.0 3.0 m ?
technical data mc68hc705j1a ? rev. 4.0 122 electrical specifications motorola electrical specifications 10.8 3.3-volt dc electrical characteristics characteristic (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min typ (2) 2. typical values at midpoint of voltage range, 25 c only max unit output voltage i load = 10.0 a i load = ? 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i load = ? 0.2 ma) pa0 ? pa7, pb0 ? pb5 v oh v dd ? 0.3 ?? v output low voltage (i load = 0.4 ma) pa0 ? pa3, pb0 ? pb5 (i load = 5.0 ma) pa4 ? pa7 v ol ?? 0.3 0.3 v input high voltage pa0 ? pa7, pb0 ? pb5, irq /v pp , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa0 ? pa7, pb0 ? pb5, irq /v pp , reset , osc1 v il v ss ? 0.2 v dd v supply current run mode (3) wait mode (4) stop mode (5) 25 c ? 40 to 105 c 3. run mode i dd is measured using external square wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 4. wait mode i dd : only timer system active. wait mode is affected linearly by osc2 capacitance. wait mode is measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v. wait mode i dd is measured using external square wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. 5. stop mode i dd is measured with osc1 = v ss . stop mode i dd is measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd ? 0.2 v i dd ? ? ? ? 1.2 0.25 0.1 1.0 4.0 1.5 5 10 ma ma a a i/o ports hi-z leakage current pa0 ? pa7, pb0 ? pb5 (without individual pulldown activated) i il ? 0.1 1 a input pulldown current pa0 ? pa7, pb0 ? pb5 (with individual pulldown activated) i il 12 30 100 a input pullup current reset i il ? 10 ? 25 ? 45 a input current (6) reset , irq /v pp , osc1 6. only input high current rated to +1 a on reset . i in ? 0.1 1 a capacitance ports (as inputs or outputs) reset , irq /v pp , osc1, osc2 c out c in ? ? ? ? 12 8 pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2 (7) 7. the r osc value selected for rc oscillator versions of this device is unspecified. see appendix c. mc68hsr705j1a for additional information. r osc 1.0 2.0 3.0 m ?
electrical specifications driver characteristics mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 123 10.9 driver characteristics figure 10-1. pa0 ? pa7, pb0 ? pb5 typical high-side driver characteristics figure 10-2. pa0 ? pa3, pb0 ? pb5 typical low-side driver characteristics notes: 1. at v dd = 5.0 v, devices are specified and tested for (v dd ? v oh ) 800 mv @ i oh = ? 0.8 ma. 2. at v dd = 3.3 v, devices are specified and tested for (v dd ? v oh ) 300 mv @ i oh = ? 0.2 ma. 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 ? 1.0 ma ? 2.0 ma ? 3.0 ma ? 4.0 ma ? 5.0 ma v dd = 5.0 v i oh v d d - v o h 8 5 c 2 5 c n o m i n a l p r o c e s s i n g ? 4 0 c 2 5 c n o m i n a l p r o c e s s i n g 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 ? 1.0 ma ? 2.0 ma ? 3.0 ma ? 4.0 ma ? 5.0 ma v dd = 3.3 v i oh v d d - v o h 8 5 c ? 4 0 c s e e n o t e 1 s e e n o t e 2 1 0 5 c 1 0 5 c 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10.0 ma v dd = 3.3 v i ol v o l 8 5 c ? 4 0 c 2 5 c n o m i n a l p r o c e s s i n g s e e n o t e 2 notes: 1. at v dd = 5.0 v, devices are specified and tested for v ol 400 mv @ i ol = 1.6 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 300 mv @ i ol = 0.4 ma. 1 0 5 c 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10.0 ma v dd = 5.0 v i ol v o l 8 5 c ? 4 0 c 2 5 c n o m i n a l p r o c e s s i n g s e e n o t e 2 1 0 5 c
technical data mc68hc705j1a ? rev. 4.0 124 electrical specifications motorola electrical specifications figure 10-3. pa4 ? pa7 typical low-side driver characteristics 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 10 ma 20 ma 30 ma 40 ma 50 ma v dd = 5.0 v i ol v o l 8 5 c 2 5 c n o m i n a l p r o c e s s i n g 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 10 ma 20 ma 30 ma 40 ma 50 ma i ol 8 5 c ? 4 0 c 2 5 c n o m i n a l p r o c e s s i n g v o l s e e n o t e 2 s e e n o t e 1 notes: 1. at v dd = 5.0 v, devices are specified and tested for v ol 400 mv @ i ol = 10.0 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 300 mv @ i ol = 5.0 ma. 1 0 5 c 1 0 5 c ? 4 0 c v dd = 3.3 v
electrical specifications typical supply currents mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 125 10.10 typical supply currents figure 10-4. typical operating i dd (25 c) figure 10-5. typical wait mode i dd (25 c) 6.0 ma 5.0 ma 4.0 ma 3.0 ma 2.0 ma 1.0 ma 0 0 1.0 mhz 2.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v s u p p l y c u r r e n t ( i d d ) notes: 1. at v dd = 5.0 v, devices are specified and tested for i dd 6.0 ma @ f op = 2.1 mhz. 2. at v dd = 3.3 v, devices are specified and tested for i dd 4.0 ma @ f op = 1.0 mhz. see note 1 see note 2 internal operating frequency (f op ) 700 a 600 a 500 a 400 a 300 a 200 a 100 a 0 0 1.0 mhz 2.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v s u p p l y c u r r e n t ( i d d ) internal operating frequency (f op ) notes: 1. at v dd = 5.0 v, devices are specified and tested for i dd 2.75 ma @ f op = 2.1 mhz. 2. at v dd = 3.3 v, devices are specified and tested for i dd 1.5 ma @ f op = 1.0 mhz. see note 1 see note 2
technical data mc68hc705j1a ? rev. 4.0 126 electrical specifications motorola electrical specifications 10.11 eprom programming characteristics 10.12 5.0-volt control timing characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min typ max unit programming voltage irq /v pp v pp 16.0 16.5 17.0 v programming current irq /v pp i pp ? 3.0 10.0 ma programming time per array byte mor t epgm t mpgm 4 4 ? ? ? ? ms characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min max unit oscillator frequency crystal oscillator option external clock source f osc ? dc 4.2 4.2 mhz internal operating frequency (f osc 2) crystal oscillator external clock f op ? dc 2.1 2.1 mhz cycle time (1 f op )t cyc 476 ? ns reset pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc irq interrupt pulse width low (edge- and level-triggered) t ilil 1.5 note (2) 2. the maximum width, t ilil or t ilih , should not be more than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc or the interrupt service routine will be re-entered. t cyc pa0 ? pa3 interrupt pulse width high (edge-triggered) t ihil 1.5 ? t cyc pa0 ? pa3 interrupt pulse width (edge- and level-triggered) t ihih 1.5 note (2) t cyc osc1 pulse width t oh , t ol 200 ? ns
electrical specifications 3.3-volt control timing mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 127 10.13 3.3-volt control timing characteristic (1) 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ? 40 c to +105 c, unless otherwise noted symbol min max unit oscillator frequency crystal oscillator option external clock source f osc ? dc 2.0 2.0 mhz internal operating frequency (f osc 2) crystal oscillator external clock f op ? dc 1.0 1.0 mhz cycle time (1 f op )t cyc 1000 ? ns reset pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilih 1.5 ? t cyc irq interrupt pulse width low (edge- and level-triggered) t ilil 1.5 note (2) 2. the maximum width, t ilil or t ilih , should not be more than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc or the interrupt service routine will be re-entered. t cyc pa0 ? pa3 interrupt pulse width high (edge-triggered) t ihil 1.5 ? t cyc pa0 ? pa3 interrupt pulse width (edge- and level-triggered) t ihih 1.5 note (2) t cyc osc1 pulse width t oh , t ol 400 ? ns
technical data mc68hc705j1a ? rev. 4.0 128 electrical specifications motorola electrical specifications figure 10-6. external interrupt timing figure 10-7. stop mode recovery timing irq (internal) t ilih t ilil t ilih irq pin irq 1 irq n . . . t ilih 4064 t cyc osc (note 1) t rl reset irq (note 2) irq (note 3) internal clock internal address bus notes : 1. internal clocking from osc1 pin 2. edge-triggered external interrupt mask option 3. edge- and level-triggered external interrupt mask option 4. reset vector shown as example reset or interrupt vector fetch 07fe 07fe 07fe 07fe 07fe 07ff (note 4)
electrical specifications 3.3-volt control timing mc68hc705j1a ? rev. 4.0 technical data motorola electrical specifications 129 figure 10-8. power-on reset timing figure 10-9. external reset timing 07fe 4064 t cyc v dd osc1 pin internal clock internal address bus notes : internal data bus 07fe 07fe 07fe 07fe 07fe 07ff (note 1) 1. power-on reset threshold is typically between 1 v and 2 v. 2. internal clock, internal address bus, and internal data bus are not available externally. new pch new pcl internal clock internal address bus notes : internal data bus 07fe 07fe 07fe 07fe 07ff new pc 1. internal clock, internal address bus, and internal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pc new pcl dummy op code
technical data mc68hc705j1a ? rev. 4.0 130 electrical specifications motorola electrical specifications
mc68hc705j1a ? rev. 4.0 technical data motorola mechanical specifications 131 technical data ? mc68hc705j1a section 11. mechanical specifications 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 11.3 plastic dual in-line package (case 738) . . . . . . . . . . . . . . . .132 11.4 small outline integrated circuit (case 751) . . . . . . . . . . . . . .132 11.5 ceramic dual in-line package (case 732) . . . . . . . . . . . . . .133 11.2 introduction the mc68hc705j1a, the resistor-capacitor (rc) oscillator, and high-speed option devices described in appendix a. mc68hrc705j1a , appendix b. mc68hsc705j1a , and appendix c. mc68hsr705j1a are available in the following packages: 738-03 ? plastic dual in-line package (pdip) 751d-04 ? small outline integrated circuit (soic) 732-03 ? ceramic dip (cerdip) (windowed)
technical data mc68hc705j1a ? rev. 4.0 132 mechanical specifications motorola mechanical specifications 11.3 plastic dual in-line package (case 738) 11.4 small outline integrated circuit (case 751)

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mechanical specifications ceramic dual in-line package (case 732) mc68hc705j1a ? rev. 4.0 technical data motorola mechanical specifications 133 11.5 ceramic dual in-line package (case 732) notes: 1. leads within 0.010 diameter, true position at seating plane, at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimensions a and b include meniscus. dim min max inches a 0.940 0.990 b 0.260 0.295 c 0.150 0.200 d 0.015 0.022 f 0.055 0.065 g 0.100 bsc h 0.020 0.050 j 0.008 0.012 k 0.125 0.160 l 0.300 bsc m 0 15 n 0.010 0.040 a 20 110 11 b f c seating plane d h g k n j m l
technical data mc68hc705j1a ? rev. 4.0 134 mechanical specifications motorola mechanical specifications
mc68hc705j1a ? rev. 4.0 technical data motorola 135 technical data ? mc68hc705j1a section 11. section 12. ordering information 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 12.3 mcu order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 12.2 introduction this section contains ordering information for the available package types. 12.3 mcu order numbers table 12-1 lists the mc order numbers. table 12-1. order numbers package type case outline pin count operating temperature order number (1) 1. refer to appendix a. mc68hrc705j1a , appendix b. mc68hsc705j1a , and appendix c. mc68hsr705j1a for ordering information on optional high-speed and resistor-capacitor oscillator devices. pdip 738-03 20 0 to 70 c ? 40 to +85 c ? 40 to +105 c mc68hc705j1ap (2) mc68hc705j1ac (3) p mc68hc705j1av (4) p 2. p = plastic dual in-line package (pdip) 3. c = extended temperature range 4. v = automotive temperature range soic 751d-04 20 0 to 70 c ? 40 to +85 c ? 40 to +105 c mc68hc705j1adw (5) mc68hc705j1acdw mc68hc705j1avdw 5. dw = small outline integrated circuit (soic) cerdip 732-03 20 0 to 70 c ? 40 to +85 c ? 40 to +105 c mc68hc705j1as (6) mc68hc705j1acs mc68hc705j1avs 6. s = ceramic dual in-line package (cerdip)
technical data mc68hc705j1a ? rev. 4.0 136 ordering information motorola ordering information
mc68hc705j1a ? rev. 4.0 technical data motorola mc68hrc705j1a 137 technical data ? mc68hc705j1a appendix a. mc68hrc705j1a a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 a.3 rc oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 a.4 typical internal operating frequency for rc oscillator option. . . . . . . . . . . . . . . . . . . . . . . . . . .139 a.5 package types and order numbers . . . . . . . . . . . . . . . . . . .140 a.2 introduction this appendix introduces the mc68hrc705j1a, a resistor-capacitor (rc) oscillator mask option version of the mc68hc705j1a. all of the information in this document applies to the mc68hrc705j1a with the exceptions given in this appendix.
technical data mc68hc705j1a ? rev. 4.0 138 mc68hrc705j1a motorola mc68hrc705j1a a.3 rc oscillator connections for greater cost reduction, the rc oscillator mask option allows the configuration shown in figure a-1 to drive the on-chip oscillator. mount the rc components as close as possible to the pins for startup stabilization and to minimize output distortion. figure a-1. rc oscillator connections note: the optional internal resistor is not recommended for configurations that use the rc oscillator connections as shown in figure a-1 . for such configurations, the oscillator internal resistor (oscres) bit of the mask option register should be programmed to a logic 0. mcu v dd v ss c1 c2 osc1 osc2 r osc1 osc2 r
mc68hrc705j1a typical internal operating frequency for rc oscillator option mc68hc705j1a ? rev. 4.0 technical data motorola mc68hrc705j1a 139 a.4 typical internal operating frequency for rc oscillator option figure a-2 shows typical internal operating frequencies at 25 c for the rc oscillator option. note: tolerance for resistance is 50%. when selecting resistor size, consider the tolerance to ensure that the resulting oscillator frequency does not exceed the maximum operating frequency. figure a-2. typical internal operating frequency for various v dd at 25 c ? rc oscillator option only 0.01 0.1 1 10 1 10 100 1000 10000 resistance (k ? ) frequency (mhz) 3.0 v 3.6 v 4.5 v 5.0 v 5.5 v
technical data mc68hc705j1a ? rev. 4.0 140 mc68hrc705j1a motorola mc68hrc705j1a a.5 package types and order numbers table a-1. mc68hrc705j1a (rc oscillator option) order numbers package type case outline pin count operating temperature order number (1) 1. refer to section 12. ordering information for standard part ordering information. pdip 738-03 20 0 to 70 c ? 40 to +85 c ? 40 to +105 c mc68hrc705j1ap (2) mc68hrc705j1ac (3) p mc68hrc705j1av (4) p 2. p = plastic dual in-line package (pdip) 3. c = extended temperature range 4. v = automotive temperature range soic 751d-04 20 0 to 70 c ? 40 to +85 c ? 40 to +105 c mc68hrc705j1adw (5) mc68hrc705j1acdw mc68hrc705j1avdw 5. dw = small outline integrated circuit (soic) cerdip 732-03 20 0 to 70 c ? 40 to +85 c ? 40 to +105 c mc68hrc705j1as (6) mc68hrc705j1acs mc68hrc705j1avs 6. s = ceramic dual in-line package (cerdip)
mc68hc705j1a ? rev. 4.0 technical data motorola mc68hsc705j1a 141 technical data ? mc68hc705j1a appendix b. mc68hsc705j1a b.1 contents b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 b.3 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .142 b.4 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .142 b.5 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 b.6 package types and order numbers . . . . . . . . . . . . . . . . . . .144 b.2 introduction this appendix introduces the mc68hsc705j1a, a high-speed version of the mc68hc705j1a. all of the information in this document applies to the mc68hsc705j1a with the exceptions given in this appendix.
technical data mc68hc705j1a ? rev. 4.0 142 mc68hsc705j1a motorola mc68hsc705j1a b.3 5.0-volt dc electrical characteristics b.4 3.3-volt dc electrical characteristics b.5 typical supply currents figure b-1. typical high-speed operating i dd (25 c) characteristic symbol min typ max unit supply current (f op = 4.0 mhz) run wait i dd ? 4.25 0.57 7.0 3.25 ma characteristic symbol min typ max unit supply current (f op = 2.1 mhz) run wait i dd ? 1.4 0.28 4.25 1.75 ma 6.0 ma 5.0 ma 4.0 ma 3.0 ma 2.0 ma 1.0 ma 0 0 1.0 mhz 2.0 mhz 3.0 mhz 4.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v s u p p l y c u r r e n t ( i d d ) internal operating frequency (f op ) notes: 1. at v dd = 5.0 v, high-speed devices are specified and tested for i dd 7.0 ma @ f op = 4.0 mhz. 2. at v dd = 3.3 v, high-speed devices are specified and tested for i dd 4.25 ma @ f op = 2.1 mhz. see note 1 see note 2 7.0 ma
mc68hsc705j1a typical supply currents mc68hc705j1a ? rev. 4.0 technical data motorola mc68hsc705j1a 143 figure b-2. typical high-speed wait mode i dd (25 c) 700 a 600 a 500 a 400 a 300 a 200 a 100 a 0 0 1.0 mhz 2.0 mhz 3.0 mhz 4.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v s u p p l y c u r r e n t ( i d d ) internal operating frequency (f op ) notes: 1. at v dd = 5.0 v, high-speed devices are specified and tested for i dd 3.25 ma @ f op = 4.0 mhz. 2. at v dd = 3.3 v, high-speed devices are specified and tested for i dd 1.75 ma @ f op = 2.1 mhz. see note 1 see note 2
technical data mc68hc705j1a ? rev. 4.0 144 mc68hsc705j1a motorola mc68hsc705j1a b.6 package types and order numbers table b-1. mc68hsc705j1a (high speed) order numbers package type case outline pin count operating temperature order number (1) 1. refer to section 12. ordering information for standard part ordering information. pdip 738-03 20 0 to 70 c ? 40 to +85 c mc68hsc705j1ap (2) mc68hsc705j1ac (3) p 2. p = plastic dual in-line package (pdip) 3. c = extended temperature range soic 751d-04 20 0 to 70 c ? 40 to +85 c mc68hsc705j1adw (4) mc68hsc705j1acdw 4. dw = small outline integrated circuit (soic) cerdip 732-03 20 0 to 70 c ? 40 to +85 c mc68hsc705j1as (5) mc68hsc705j1acs 5. s = ceramic dual in-line package (cerdip)
mc68hc705j1a ? rev. 4.0 technical data motorola mc68hsr705j1a 145 technical data ? mc68hc705j1a appendix c. mc68hsr705j1a c.1 contents c.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 c.3 rc oscillator connections (external resistor). . . . . . . . . . . . 145 c.4 typical internal operating frequency at 25 c for high-speed rc oscillator option. . . . . . . . . . . . . . . . . 146 c.5 rc oscillator connections (no external resistor) . . . . . . . . .147 c.6 typical internal operating frequency versus temperature (no external resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 c.7 package types and order numbers . . . . . . . . . . . . . . . . . . .149 c.2 introduction this appendix introduces the mc68hsr705j1a, a high-speed version of the mc68hrc705j1a. all of the information in this document applies to the mc68hsr705j1a with the exceptions given in this appendix. c.3 rc oscillator connections (external resistor) refer to appendix a. mc68hrc705j1a for a description of the resistor-capacitor (rc) oscillator connections with external resistor.
technical data mc68hc705j1a ? rev. 4.0 146 mc68hsr705j1a motorola mc68hsr705j1a c.4 typical internal operating frequency at 25 c for high-speed rc oscillator option figure c-1. typical internal operating frequency at 25 c for high-speed rc oscillator option for lower frequency operation characteristics, refer to appendix a. mc68hrc705j1a . note: tolerance for resistance is 50 percent. when selecting resistor size, consider the tolerance to ensure that resulting oscillator frequency does not exceed the maximum operating frequency. 1 10 1 10 100 resistance (k ? ) frequency (mhz) 3.0 v 3.6 v 4.5 v 5.0 v 5.5 v
mc68hsr705j1a rc oscillator connections (no external resistor) mc68hc705j1a ? rev. 4.0 technical data motorola mc68hsr705j1a 147 c.5 rc oscillator connections (no external resistor) for maximum cost reduction, the rc oscillator mask connections shown in figure c-2 allow the on-chip oscillator to be driven with no external components. this can be accomplished by programming the oscillator internal resistor (oscres) bit in the mask option register to a logic 1. when programming the oscres bit for the mc68hsr705j1a, an internal resistor is selected which yields typical internal oscillator frequencies as shown in figure c-3 . the internal resistance for this device is different than the resistance of the selectable internal resistor on the mc68hc705j1a and the mc68hsc705j1a devices. note: this option is not available on the rom version of this device (mc68hc05j1a). figure c-2. rc oscillator connections (no external resistor) mcu v dd v ss c1 c2 osc1 osc2 osc1 osc2 r external connections left open
technical data mc68hc705j1a ? rev. 4.0 148 mc68hsr705j1a motorola mc68hsr705j1a c.6 typical internal operating frequency versus temperature (no external resistor) figure c-3. typical internal operating frequency versus temperature (oscres bit = 1) note: due to process variations, operating voltages, and temperature requirements, the internal resistance and tolerance are unspecified. typically for a given voltage and temperature, the frequency should not vary more than 500 khz. however, this data is not guaranteed. it is the user?s responsibility to ensure that the resulting internal operating frequency meets the user?s requirements. 3.0 v 3.6 v 4.5 v 5.0 v 5.5 v frequency (mhz) temperature ( c) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 ? 50 0 50 100 150
mc68hsr705j1a package types and order numbers mc68hc705j1a ? rev. 4.0 technical data motorola mc68hsr705j1a 149 c.7 package types and order numbers table c-1 . mc68hsr705j1a (high-speed rc oscillator option) order numbers (1) 1. refer to section 12. ordering information for standard part ordering information. package type case outline pin count operating temperature order number pdip 738-03 20 0 to 70 c ? 40 to +85 c mc68hsr705j1ap (2) mc68hsr705j1ac (3) p 2. p = plastic dual in-line package (pdip) 3. c = extended temperature range soic 751d-04 20 0 to 70 c ? 40 to +85 c mc68hsr705j1adw (4) mc68hsr705j1acdw 4. dw = small outline integrated circuit (soic) cerdip 732-03 20 0 to 70 c ? 40 to +85 c mc68hsr705j1as (5) mc68hsr705j1acs 5. s = ceramic dual in-line package (cerdip)
technical data mc68hc705j1a ? rev. 4.0 150 mc68hsr705j1a motorola mc68hsr705j1a
mc68hc705j1a ? rev. 4.0 technical data motorola index 151 technical data ? mc68hc705j1a index a accumulator register (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 b block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 c c bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 computer operating properly (cop) module . . . . . . . . . . . . . . . . . . . 97 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 cop in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 cop in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 cop register (copr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 cop reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 copen bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
technical data mc68hc705j1a ? rev. 4.0 152 index motorola index cpu registers accumulator register (a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 program counter register (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 stack pointer register (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 d data direction registers data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . 90 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . 93 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 e elat bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 , 127 dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . 121 , 122 driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 mc68hsc705j1a (high-speed option) . . . . . . . . . . . . . . . . . . . 142 mc68hsr705j1a (high-speed rc oscillator option) . . . . . . . . 145 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 electrostatic damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 epgm bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 epmsec bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 eprom eprom security programmable option . . . . . . . . . . . . . . . . . . . . 25 eprom/otprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 40 programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 programming register (eprog). . . . . . . . . . . . . . . . . . . . . . . . . . 39
index mc68hc705j1a ? rev. 4.0 technical data motorola index 153 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 external interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 external reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 g general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 h h bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 i i bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupts external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 , 74 external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 external interrupt module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 , 107 external interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 interrupt flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 , 103 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 irq module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 irq status and control register (iscr) . . . . . . . . . . . . . . . . . . . 106 irq /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 104 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 optional external interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 pin sensitivity selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 pin triggering option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 port a external interrupts programmable option. . . . . . . . . . . . . . 25
technical data mc68hc705j1a ? rev. 4.0 154 index motorola index real-time interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 77 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 software interrupt vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 , 112 timer overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 irq latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 irq /v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 98 , 104 irqe bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 irqf bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 irqr bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 j junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 l level bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 cop timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 , 84 effects on clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 effects on cop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 effects on cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 effects on eprom/otprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 flowchart (stop/halt/wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 stop instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 , 82 stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 timing of stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
index mc68hc705j1a ? rev. 4.0 technical data motorola index 155 m mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 mc68hc705j1a features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mc68hrc705j1a (rc oscillator option) . . . . . . . . . . . . . . . . . . . . 137 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 rc oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 mc68hsc705j1a (high-speed option) . . . . . . . . . . . . . . . . . . . . . . 141 dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 typical operating current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 typical wait mode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 mc68hsr705j1a (high-speed rc oscillator option) . . . . . . . . . . . 145 operating frequencies (with oscres bit set) . . . . . . . . . . . . . . 148 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 rc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 rc oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 eprom/otprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 eprom/otprom programming . . . . . . . . . . . . . . . . . . . . . . . . . 38 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mask option register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 mpgm bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 multifunction timer module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 n n bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
technical data mc68hc705j1a ? rev. 4.0 156 index motorola index o opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 options (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 options (programmable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 mc68hrc705j1a (rc oscillator option) . . . . . . . . . . . . . . . . . . 140 mc68hsc705j1a (high-speed option) . . . . . . . . . . . . . . . . . . . 144 mc68hsr705j1a (high-speed rc oscillator option) . . . . . . . . 149 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 140 , 144 , 149 osc1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 osc2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 oscillator crystal oscillator internal resistor option . . . . . . . . . . . . . . . . . . . . 25 delay counter programmable option. . . . . . . . . . . . . . . . . . . . . . . 25 on-chip oscillator stabilization delay. . . . . . . . . . . . . . . . . . . . . . . 71 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 oscres bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 p pa0 ? pa3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 parallel input/output (i/o) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pirq bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port a data direction register (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 data register (porta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 i/o pin interrupts (pa0 ? pa3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 led drive capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pulldown register (pdra). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 port b data direction register (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
index mc68hc705j1a ? rev. 4.0 technical data motorola index 157 i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 port b data register (portb). . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 pulldown register (pdrb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 programming model (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pulldown register a (pdra). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pulldown register b (pdrb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 pulldown resistors programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 r ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 stack ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 registers cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 parallel i/o port register summary . . . . . . . . . . . . . . . . . . . . . . . . 88 reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 72 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 cop register (copr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 cop watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 external reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 illegal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 power-on reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 77 resistors (pulldown) programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 rt1, rt0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
technical data mc68hc705j1a ? rev. 4.0 158 index motorola index rtie bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 rtif bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 rtifr bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 s schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 104 , 105 soscd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 stack pointer register (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 , 100 , 106 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 , 100 effect on cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 stop instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 stop/halt mode programmable option . . . . . . . . . . . . . . . . . . . . . . . . 25 swait bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 swpdi bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 t thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 , 112 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 timer status and control register (tscr) . . . . . . . . . . . . . . . . . . 112 tof bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 tofr bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 toie bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
index mc68hc705j1a ? rev. 4.0 technical data motorola index 159 v v dd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v ss pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 w wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 , 100 , 106 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 z z bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
technical data mc68hc705j1a ? rev. 4.0 160 index motorola index

how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 mc68hc705j1a/d

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